P o w e r-S u p p ly Mo n it o r w it h Re s e t
____________________P in De s c rip t io n
150
T = +25°C
A
PIN
NAME
FUNCTION
No Connect. There is no internal
connection to this pin.
1, 4, 5,
6, 8
N.C.
VCC
100
50
0
2
3
+5V, +3.3V, or +3V Supply Voltage
Ground
MAX709L/M
GND
MAX709
10ns
Reset Output remains low while VCC is
below the reset threshold, and for
280ms after VCC rises above the reset
threshold.
MAX709R/S/T
7
RESET
10
100
1k
10k
RESET COMPARATOR OVERDRIVE, V - V (mV)
TH
CC
Figure 1. Ma ximum Tra ns ie nt Dura tion without Ca us ing a
Reset Pulse vs. Reset Comparator Overdrive
__________Ap p lic a t io n s In fo rm a t io n
Ne g a t ive -Go in g VCC Tra n s ie n t s
In addition to issuing a reset to the microprocessor
(µP) during power-up, power-down, and brownout con-
ditions, the MAX709 is relatively immune to short dura-
tion negative-going VCC transients (glitches).
A 0.1µF bypass capacitor mounted as close as possible
to pin 2 (VCC) provides additional transient immunity.
En s u rin g a Va lid RES ET Ou t p u t
Do w n t o VCC = 0 V
Figure 1 shows typical transient duration vs. reset com-
parator overdrive, for which the MAX709 does not gen-
erate a reset pulse. The graph was generated using a
negative-going pulse applied to VCC, starting 1.5V
above the actual reset threshold and ending below it
by the magnitude indicated (reset comparator over-
drive). The graph indicates the typical maximum pulse
width that a negative-going VCC transient may have
without causing a reset pulse to be issued. As the
magnitude of the transient increases (goes farther
below the reset threshold), the maximum allowable
When VCC falls below 1V, the MAX709 RESET output
no longer sinks current—it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
nected to the RESET output can drift to undermined
voltages. This presents no problem in most applica-
tions, since most µP and other circuitry is inoperative
with VCC below 1V. However, in applications where the
RESET output must be valid down to 0V, adding a pull-
down resistor to the RESET pin will cause any stray
leakage currents to flow to ground, holding RESET low
(see Figure 2). The resistance value of R1 is not criti-
cal. It should be about 100kΩ, which is large enough
not to load RESET and small enough to pull RESET to
ground.
p uls e wid th d e c re a s e s .
Typ ic a lly, for the
MAX709L/MAX709M, a VCC transient that goes 100mV
below the reset threshold and lasts 40µs or less will not
cause a reset pulse to be issued.
4
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