Lo w -Co s t , µP S u p e rvis o ry Circ u it s
WATCHDOG
TRANSITION
DETECTOR
6
WATCHDOG
TIMER
8
7
5
WDI
8
7
WDO
V
CC
RESET
RESET
V
CC
250µA
TIMEBASE FOR
RESET AND
WATCHDOG
1
2
MR
250µA
1
2
MR
RESET
GENERATOR
V
CC
RESET
GENERATOR
RESET
(RESET)
V
CC
MAX707
MAX708
4.65V*
1.25V
MAX705
MAX706
MAX813L
4.65V*
1.25V
4
PFI
5
4
PFO
PFI
PFO
3
GND
3
GND
* 4.40V FOR MAX7O6.
( ) ARE FOR MAX813L ONLY.
* 4.40V FOR MAX7O6.
Figure 1. MAX705/MAX706/MAX813L Block Diagram
Figure 2. MAX707/MAX708 Block Diagram
WDI input is three-stated, the watchdog timer will stay
cleared and will not count. As soon as reset is released
and WDI is driven high or low, the timer will start counting.
Pulses as short as 50ns can be detected.
_______________De t a ile d De s c rip t io n
5–70/MAX813L
Re s e t Ou t p u t
A microprocessor’s (µP’s) reset input starts the µP in a
known state. Whenever the µP is in an unknown state, it
should be held in reset. The MAX705-MAX708/MAX813L
assert reset during power-up and prevent code execu-
tion errors during power-down or brownout conditions.
Typically, WDO will be connected to the non-maskable
interrupt input (NMI) of a µP. When VCC drops below
the reset threshold, WDO will go low whether or not the
watchdog timer has timed out yet. Normally this would
trigger an NMI interrupt, but RESET goes low simultane-
ously, and thus overrides the NMI interrupt.
On power-up, once VCC reaches 1V, RESET is a guaran-
teed logic low of 0.4V or less. As V rises, RESET stays
low. When VCC rises above the resCeCt threshold, an inter-
nal timer releases RESET after about 200ms. RESET puls-
es low whenever VCC dips below the reset threshold, i.e.
brownout condition. If brownout occurs in the middle of
a previously initiated reset pulse, the pulse continues for
at least another 140ms. On power-down, once V falls
below the reset threshold, RESET stays low and iCs Cguar-
If WDI is left unconnected, WDO can be used as a low-
line output. Since floating WDI disables the internal
timer, WDO goes low only when VCC falls below the
reset threshold, thus functioning as a low-line output.
The MAX705/MAX706 have a watchdog timer and a
RESET output. The MAX707/MAX708 have both active-
high and active-low reset outputs. The MAX813L has
both an active-high reset output and a watchdog timer.
anteed to be 0.4V or less until V drops below 1V.
CC
The MAX707/MAX708/MAX813L active-high RESET output
is simply the complement of the RESET output, and is
guaranteed to be valid with V down to 1.1V. Some µPs,
such as Intel’s 80C51, requireCaCn active-high reset pulse.
Ma n u a l Re s e t
The manual-reset input (MR) allows reset to be trig-
gered by a pushbutton switch. The switch is effectively
debounced by the 140ms minimum reset pulse width.
MR is TTL/CMOS logic compatible, so it can be driven
by an external logic line. MR can be used to force a
wa tc hd og time out to g e ne ra te a re s e t p uls e in the
MAX705/MAX706/MAX813L. Simply connect WDO to
MR.
Wa t c h d o g Tim e r
The MAX705/MAX706/MAX813L watchdog circuit moni-
tors the µP’s activity. If the µP does not toggle the watch-
dog input (WDI) within 1.6sec and WDI is not three-stat-
ed, WDO goes low. As long as RESET is asserted or the
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