+3V Voltage Monitoring, Low-Cost µP
Supervisory Circuits
MAX706P/R/S/T, MAX706AP/AR/AS/AT, MAX708R/S/T
WDI
6
WATCHDOG
TRANSITION
DETECTOR
V
CC
70µA
WATCHDOG
TIMER
8
WDO
V
CC
70µA
MR
1
2
RESET
GENERATOR
8
RESET
TIMEBASE FOR
RESET AND
WATCHDOG
7
MR
1
2
RESET
GENERATOR
V
CC
RESET
(RESET)
7
RESET
V
CC
PFI
4
2.63V MAX706P/R
2.93V MAX706S
MAX706P/R/S/T
3.08V MAX706T
MAX706AP/AR/AS/AT
5
PFO
PFI
4
2.63V MAX708R
2.93V MAX708S
3.08V MAX708T
MAX708R/S/T
5
PFO
1.25V
1.25V
3 GND
( ) ARE FOR MAX706P/AP.
3 GND
Figure 1. MAX706_ Functional Diagram
Figure 2. MAX708_ Functional Diagram
RESET and
RESET
Outputs
A microprocessor’s (µP’s) reset input starts in a known
state. When the µP is in an unknown state, it should be
held in reset. The MAX706P/R/S/T and the MAX706AP/
AR/AS/AT assert reset when V
CC
is low, preventing
code execution errors during power-up, power-down,
or brownout conditions.
On power-up once V
CC
reaches 1V,
RESET
is guaran-
teed to be logic-low and RESET is guaranteed to be
logic-high. As V
CC
rises,
RESET
and RESET remain
asserted. Once V
CC
exceeds the reset threshold, the
internal timer causes
RESET
and RESET to be
deasserted after a time equal to the reset pulse width,
which is typically 200ms (Figure 3).
If a power-fail or brownout condition occurs (i.e., V
CC
drops below the reset threshold),
RESET
and RESET
are asserted. As long as V
CC
remains below the reset
threshold, the internal timer is continually reset, causing
the
RESET
and RESET outputs to remain asserted.
Thus, a brownout condition that interrupts a previously
initiated reset pulse causes an additional 200ms delay
from the time the latest interruption occurred. On
power-down once V
CC
drops below the reset threshold,
RESET
and RESET are guaranteed to be asserted for
V
CC
≥
1V.
The MAX706P/MAX706AP provide a RESET signal, and
the MAX706R/S/T and MAX706AR/AS/AT provide a
RESET
signal. The MAX708R/S/T provide both RESET
and
RESET.
Watchdog Timer
The MAX706P/R/S/T and the MAX706AP/AR/AS/AT
watchdog circuit monitor the µP’s activity. If the µP
does not toggle the watchdog input (WDI) within 1.6s,
the watchdog output (WDO) goes low (Figure 4). If the
reset signal is asserted, the watchdog timer will be
reset to zero and disabled. As soon as reset is
released, the timer starts counting. WDI can detect puls-
es as narrow as 100ns with a 2.7V supply and 50ns with a
4.5V supply. The watchdog timer for the MAX706P/R/S/T
cannot be disabled. The watchdog timer for the
MAX706AP/AR/AS/AT operates similarly to the
MAX706P/R/S/T. However, the watchdog timer for the
MAX706AP/AR/AS/AT disables when the WDI input is
left open or connected to a tri-state output in its high-
impedance state and with a leakage current of less
than 600nA. The watchdog timer can be disabled any-
time, provided
WDO
is not asserted.
7
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