+3V Voltage Monitoring, Low-Cost µP
Supervisory Circuits
MAX706P/R/S/T, MAX706AP/AR/AS/AT, MAX708R/S/T
Pin Description
PIN
MAX706P
MAX706AP
SO/DIP
µMAX
MAX706R/S/T,
MAX706AR/AS/AT
SO/DIP
µMAX
MAX708R/S/T
SO/DIP µMAX
Active-Low, Manual-Reset Input. Pull
MR
below 0.6V to trigger a
reset pulse.
MR
is TTL/CMOS compatible when V
CC
= 5V and can
be shorted to GND with a switch.
MR
is internally connected to a
70µA source current. Connect to V
CC
or leave unconnected.
Supply Voltage Input
Ground
Adjustable Power-Fail Comparator Input. Connect PFI to a
resistive divider to set the desired PFI threshold. When PFI is
less than 1.25V,
PFO
goes low and sinks current; otherwise,
PFO
remains high. Connect PFI to GND if not used.
Active-Low, Power-Fail Comparator Output.
PFO
asserts when
PFI is below the internal 1.25V threshold.
PFO
deasserts when
PFI is above the internal 1.25V threshold. Leave
PFO
unconnected if not used.
Watchdog Input. A falling or rising transition must occur at
WDI within 1.6s to prevent
WDO
from asserting (see Figure 4).
The internal watchdog timer is reset to zero when reset is
asserted or when transition occurs at WDI. The watchdog
function for the MAX706P/R/S/T can not be disabled. The
watchdog timer for the MAX706AP/AR/AS/AT disables when
WDI input is left open or connected to a tri-state output in its
high-impedance state with a leakage current of less than
600nA.
NAME
FUNCTION
1
3
1
3
1
3
MR
2
3
4
5
2
3
4
5
2
3
4
5
V
CC
GND
4
6
4
6
4
6
PFI
5
7
5
7
5
7
PFO
6
8
6
8
—
—
WDI
7
1
—
—
8
2
Active-High Reset Output. Reset remains high when V
CC
is
RESET below the reset threshold or
MR
is held low. It remains low for
200ms after the reset conditions end (Figure 3).
Active-Low Watchdog Output.
WDO
goes low when a
transition does not occur at WDI within 1.6s and remains low
until a transition occurs at WDI (indicating the watchdog
interrupt has been serviced).
WDO
also goes low when V
CC
falls below the reset threshold; however, unlike the reset
output signal,
WDO
goes high as soon as V
CC
rises above
the reset threshold.
8
2
8
2
—
—
WDO
—
—
—
—
7
—
1
—
7
6
1
8
Active-Low Reset Output.
RESET
remains low when V
CC
is
RESET
below the reset threshold or
MR
is held low. It remains low for
200ms after the reset conditions end (Figure 3).
N.C.
No Connection. Not internally connected.
6
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