Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
Ba c k u p -Ba t t e ry Re p la c e m e n t
The backup battery may be disconnected while VCC is
above the reset threshold. No precautions are neces-
sary to avoid spurious reset pulses.
100
80
V
= 5V
CC
T = +25°C
A
0.1µF CAPACITOR
FROM V TO GND
Ne g a t ive -Go in g V
Tra n s ie n t s
CC
OUT
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration, negative-going VCC
transients (glitches). It is usually undesirable to reset
the µP when VCC experiences only small glitches.
60
40
Figure 13 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going VCC pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (reset com-
parator overdrive). The graph shows the maximum
pulse width a negative-going VCC transient may typical-
ly have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that
goes 100mV below the reset threshold and lasts for
40µs or less will not cause a reset pulse to be issued.
20
0
10
100
RESET COMPARATOR OVERDRIVE,
(Reset Threshold Voltage - V ) (mV)
1000
10000
CC
Figure 13. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
parator. Select the ratio of R1 and R2 such that PFI sees
1.25V when V falls to the desired trip point (VTRIP).
Resistor R3 adIdNs hysteresis. It will typically be an order
of ma g nitud e g re a te r tha n R1 or R2. The c urre nt
through R1 and R2 should be at least 1µA to ensure that
the 25nA (max) PFI input current does not shift the trip
point. R3 should be larger than 10kΩ to prevent it from
loading down the PFO pin. Capacitor C1 adds noise
rejection.
A 100nF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
Co n n e c t in g a Tim in g Ca p a c it o r a t OS C IN
When OSC SEL is connected to ground, OSC IN dis-
connects from its internal 10µA (typ) pull-up and is
inte rna lly c onne c te d to a ± 100nA c urre nt s ourc e .
When a capacitor is connected from OSC IN to ground
(to select alternative reset and watchdog timeout peri-
ods), the current source charges and discharges the
timing capacitor to create the oscillator that controls the
reset and watchdog timeout period. To prevent timing
errors or oscillator start-up problems, minimize external
current leakage sources at this pin, and locate the
capacitor as close to OSC IN as possible. The sum of
PC-board leakage plus OSC capacitor leakage must be
small compared to ±100nA.
Mo n it o rin g a Ne g a t ive Vo lt a g e
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 12’s circuit. When
the negative supply is valid, PFO is low. When the neg-
ative supply voltage drops, PFO goes high. This cir-
c uit’s a c c ura c y is a ffe c te d b y the PFI thre s hold
tolerance, the VCC voltage, and resistors R1 and R2.
1693L/AX80M
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
