+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
MAX6301–MAX6304
V
CC
V
CC
R1
RESET IN
V
CC
0.1µF
GND
V
CC
µP
RESET TO
OTHER SYSTEM
COMPONENTS
MAX6301
V
CC
0.1µF
4.7k
R2
MAX6301
MAX6302
MAX6303
MAX6304
RESET
RESET
Figure 6. Adding a Manual Reset Function
Figure 7. Interfacing to µPs with Bidirectional Reset I/O Pins
Interfacing to µPs with
Bidirectional Reset Pins
Since
RESET
is open-drain, the MAX6301 interfaces
easily with µPs that have bidirectional reset pins, such
as the Motorola 68HC11 (Figure 7). Connecting
RESET
directly to the µP’s reset pin with a single pull-up allows
either device to assert reset.
TO RESET
GENERATOR
WDI
WATCHDOG
TIMER
Negative-Going V
CC
Transients
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration negative-going
transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the
Typical
Operating Characteristics
shows this relationship.
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-
going pulse applied to V
IN
, starting above the actual
reset threshold (V
RST
) and ending below it by the mag-
nitude indicated (reset-threshold overdrive). As the
magnitude of the transient increases (farther below the
reset threshold), the maximum allowable pulse width
decreases. Typically, a V
CC
transient that goes 100mV
below the reset threshold and lasts 50µs or less will not
cause a reset pulse to be issued.
MAX6301
MAX6302
TO MODE
MAX6303
CONTROL
MAX6304
WDS
Figure 8. Watchdog Input Structure
Watchdog Input Current
Extended Mode
In extended mode (WDS = V
CC
), the WDI input is inter-
nally driven through a buffer and series resistor from
the watchdog counter (Figure 8). When WDI is left
unconnected, the watchdog timer is serviced within the
watchdog timeout period by a very brief low-high-low
pulse from the counter chain. For minimum watchdog
input current (minimum overall power consumption),
leave WDI low for the majority of the watchdog timeout
period, pulsing it low-high-low (>30ns) once within the
period to reset the watchdog timer. If instead WDI is
externally driven high for the majority of the timeout
period, typically 70µA can flow into WDI.
Normal Mode
In normal mode (WDS = GND), the internal buffer that
drives WDI is disabled. In this mode, WDI is a standard
CMOS input and leakage current is typically 100pA,
regardless of whether WDI is high or low.
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9
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
