+5V, Low-Power µP Supervisory Circuits
with Adjustable Reset/Watchdog
MAX6301–MAX6304
V
CC
WDI
0V
V
CC
RESET
0V
NORMAL MODE (WDS = GND)
t
WD
t
RP
Figure 2a. Watchdog Timing Diagram, WDS = GND
V
CC
WDI
0V
V
CC
RESET
0V
EXTENDED MODE (WDS = V
CC
)
t
WD
x 500
t
RP
Figure 2b. Watchdog Timing Diagram, WDS = V
CC
timeout period, then momentarily pulses high, resetting
the watchdog counter. When WDI is left unconnected,
the watchdog timer is cleared by this internal driver just
before the timeout period is reached (the internal driver
pulls WDI high at about 94% of t
WD
). When WDI is
three-stated, the maximum allowable leakage current of
the device driving WDI is 10µA.
In normal mode (WDS = GND), the watchdog timer
cannot be disabled by three-stating WDI. WDI is a
high-impedance input in this mode. Do not leave WDI
unconnected in normal mode.
V
CC
GND
V
CC
0.1µF
MAX6301
MAX6302
MAX6303
SWT
MAX6304
SRT
C
SRT
C
SWT
C
RST
= t
RP
2.67
C
RST
in pF
t
WD
in µs
t
C
SWT
=
WD
2.67
C
SWT
in pF
t
WD
in µs
Figure 3. Calculating the Reset (C
SRT
) and Watchdog
(C
SWT
) Timeout Capacitor Values
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7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
