5V, Low-Power, Voltage-Output
Serial 10-Bit DACs
MAX504/MAX515
____________________Pin Description
PIN
NAME
MAX504
MAX515
—
1
—
2
3
4
—
5
6
—
—
7
8
—
BIPOFF
DIN
CLR
SCLK
CS
DOUT
DGND
AGND
REFIN
REFOUT
V
SS
VOUT
V
DD
RFB
Bipolar offset/gain
resistor
Serial data input
Clear. Asynchronously sets
DAC register to all 0s.
Serial clock input
Chip select, active low
Serial data output for
daisy-chaining
Digital ground
Analog ground
Reference input
Reference output,
2.048V. Connect to V
DD
if not used.
Negative power supply
DAC output
Positive power supply
Feedback resistor
FUNCTION
_______________Detailed Description
General DAC Discussion
The MAX504/MAX515 use an “inverted” R-2R ladder net-
work with a single-supply CMOS op amp to convert 10-bit
digital data to analog voltage levels (see
Functional
Diagram).
The term “inverted” describes the ladder net-
work because the REFIN pin in current-output DACs is the
summing junction, or virtual ground, of an op amp.
However, such use would result in the output voltage
being the inverse of the reference voltage. The
MAX504/MAX515’s topology makes the output the same
polarity as the reference input.
An internal reset circuit forces the DAC register to reset
to all 0s on power-up. Additionally, a clear (CLR) pin,
when held low, sets the DAC register to all 0s.
CLR
operates asynchronously and independently from the
chip select (CS) pin.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Buffer Amplifier
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 10-bit performance.
Settling time is 25µs to 0.01% of final value. The output is
short-circuit protected and can drive a 2kΩ load with more
than 100pF load capacitance.
CS
t
CSH0
t
CSS
SCLK
t
DH
t
DS
DIN
t
DO
DOUT
t
CS1
t
CH
t
CL
t
CSH1
t
CSW
Figure 1. Timing Diagram
8
_______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
