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MAX494CSD 参数 Datasheet PDF下载

MAX494CSD图片预览
型号: MAX494CSD
PDF下载: 下载PDF文件 查看货源
内容描述: 单/双/四路,微功耗,单电源轨至轨运算放大器 [Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op Amps]
分类和应用: 运算放大器
文件页数/大小: 16 页 / 232 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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S in g le /Du a l/Qu a d , Mic ro p o w e r,  
S in g le -S u p p ly Ra il-t o -Ra il Op Am p s  
2/MAX495  
the op amp in an inverting configuration (Figure 3a);  
(Fig ure 4). The d iod e s limit the d iffe re ntia l volta g e  
applied to the amplifiers internal circuitry to no more  
than V , where V is the diodes forward-voltage drop  
connect resistor R3 between the noninverting input and  
the input signal when using the op amp in a noninvert-  
ing configuration (Figure 3b). Select R3 to equal the  
parallel combination of R1 and R2. High source resis-  
tances will degrade noise performance, due to the ther-  
mal noise of the resistor and the input current noise  
(which is multiplied by the source resistance).  
F
F
(about 0.7V at +25°C).  
Input bias current for the ICs (±25nA typical) is speci-  
fied for the small differential input voltages. For large  
differential input voltages (exceeding V ), this protec-  
F
tion circuitry increases the input current at IN+ and IN-:  
In p u t S t a g e P ro t e c t io n Circ u it ry  
The MAX492/MAX494/MAX495 include internal protec-  
tion circuitry that prevents damage to the precision  
input stage from large differential input voltages. This  
protection circuitry consists of back-to-back diodes  
between IN+ and IN- with two 1.7kresistors in series  
(V + - V - ) - V  
F
IN  
IN  
Input Current = ———————————  
2 x 1.7kΩ  
For comparator applications requiring large differential  
voltages (greater than V ), you can limit the input cur-  
F
rent that flows through the diodes with external resistors  
MAX492  
MAX494  
MAX495  
R2  
TO INTERNAL  
CIRCUITRY  
1.7kΩ  
IN+  
IN–  
R1  
V
IN  
V
OUT  
MAX49_  
R3  
R3 = R2 R1  
II  
TO INTERNAL  
CIRCUITRY  
1.7kΩ  
Figure 3a. Reducing Offset Error Due to Bias Current:  
Inverting Configuration  
Figure 4. Input Stage Protection Circuitry  
10,000  
R3  
V
IN  
UNSTABLE REGION  
V
OUT  
MAX49_  
R2  
R1  
1000  
R3 = R2 R1  
II  
V
V
OUT  
= +5V  
= V /2  
CC  
CC  
R TO V  
L
EE  
A = +1  
V
100  
1
10  
RESISTIVE LOAD (k)  
100  
Figure 3b. Reducing Offset Error Due to Bias Current:  
Noninverting Configuration  
Figure 5. Capacitive-Load Stable Region Sourcing Current  
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