±1 5 k V ES D-P ro t e c t e d , S le w -Ra t e -Lim it e d ,
Lo w -P o w e r, RS -4 8 5 /RS -4 2 2 Tra n s c e ive rs
MAX481E
0.1µF
MAX483E
TOP VIEW
DE
MAX485E
MAX487E
MAX1487E
DI
R
R
1
2
3
4
RO
RE
DE
DI
1
2
3
4
RO
RE
DE
DI
8
8
7
6
5
V
CC
B
Rt
V
D
CC
B
A
7
B
Rt
6
A
A
RO
R
D
D
5
GND
GND
RE
DIP/SO
NOTE: PIN LABELS Y AND Z ON TIMING, TEST, AND WAVEFORM DIAGRAMS REFER TO PINS A AND B WHEN DE IS HIGH.
TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE.
Figure 1. MAX481E/MAX483E/MAX485E/MAX487E/MAX1487E Pin Configuration and Typical Operating Circuit
0.1µF
V
CC
V
CC
1
MAX488E
MAX490E
Y
Z
5
6
TOP VIEW
3
2
Rt
DI
RO
DI
D
R
V
1
2
3
4
R
8
7
6
5
A
B
Z
CC
RO
DI
8
7
A
B
Rt
RO
R
D
GND
Y
D
DIP/SO
4
GND
GND
NOTE: TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE.
Figure 2. MAX488E/MAX490E Pin Configuration and Typical Operating Circuit
V
CC
DE
V
CC
RE
TOP VIEW
0.1µF
4
14
MAX489E
MAX491E
N.C.
1
2
3
4
5
6
7
14
V
CC
9
Y
R
RO
RE
13 N.C.
5
Rt
DI
RO
D
R
10
12
11
10
9
A
Z
DE
B
12
11
A
2
Rt
DI
Z
RO
NC
R
D
DI
D
GND
GND
Y
B
1, 8, 13
8
N.C.
3
6, 7
GND
DIP/SO
Figure 3. MAX489E/MAX491E Pin Configuration and Typical Operating Circuit
_______________________________________________________________________________________
RE
GND DE
35–9/MAX1487E
8
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
