±1 5 k V ES D-P ro t e c t e d , S le w -Ra t e -Lim it e d ,
Lo w -P o w e r, RS -4 8 5 /RS -4 2 2 Tra n s c e ive rs
35–9/MAX1487E
3V
DE
C
L1
A
B
V
CC
Y
Z
S1
S2
500Ω
R
RO
DIFF
DI
OUTPUT
UNDER TEST
V
ID
RE
C
L
C
L2
Figure 10. Driver/Receiver Timing Test Circuit
Figure 11. Driver Timing Test Load
3V
3V
DE
DI
1.5V
1.5V
1.5V
1.5V
0V
0V
t
t
PHL
PLH
1/2 V
O
t
LZ
t
, t
ZL(SHDN) ZL
Z
Y, Z
V
2.3V
V
+0.5V
O
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
V
OL
Y
1/2 V
O
V
= V (Y) - V (Z)
DIFF
Y, Z
0V
V
O
V
OH
-0.5V
2.3V
V
DIFF
90%
90%
0V
-V
10%
10%
O
t
, t
t
HZ
ZH(SHDN) ZH
t
R
t
F
t
| t - t
|
SKEW = PLH PHL
Figure 12. Driver Propagation Delays
Figure 13. Driver Enable and Disable Times (except MAX488E
and MAX490E)
3V
RE
1.5V
1.5V
0V
V
OH
t
t
, t
RO
LZ
ZL(SHDN) ZL
1.5V
1.5V
0V
V
OL
OUTPUT
V
RO
CC
1.5V
V
+ 0.5V
- 0.5V
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
t
t
PLH
PHL
V
ID
A-B
0V
-V
INPUT
ID
RO
V
OH
1.5V
0V
t
, t
t
HZ
ZH(SHDN) ZH
Figure 14. Receiver Propagation Delays
Figure 15. Receiver Enable and Disable Times (except MAX488E
and MAX490E)
______________________________________________________________________________________ 11