Fo rc e -S e n s e S w it c h e s
/MAX456
S w it c h in g Gu a rd e d a n d
Fo rc e -S e n s e S ig n a ls
S w it c h Re s is t a n c e s
Each IC contains four internal switches: four low-current
s e ns e -g ua rd s witc he s a nd two hig h-c urre nt forc e
switches. Each sense-guard switch has an on-resis-
tance of approximately 60Ω, while each force switch
ha s a n on-re s is ta nc e of a p p roxima te ly 6Ω. The
MAX4555’s two low-current sense-guard switches are
connected in parallel to produce lower on-resistance
and allow higher current.
When a precision source or measurement must be con-
nected sequentially to several circuits, all sense and
guard connections must be switched simultaneously,
a nd a t le a s t one of the forc e c onne c tions mus t b e
switched. To maintain safety and low noise levels, the
ground (or chassis) connection should never be dis-
connected.
The force circuit switch should have low-resistance,
high-current capability, but the sense and guard circuit
switches require only moderate resistance and current
capability. The sense and guard switches should have
lowe r le a ka g e tha n the lowe s t me a s ure d c urre nt.
CMOS switches should also be operated from power
supplies higher than the highest circuit voltage to be
switched.
P o w e r-S u p p ly Co n s id e ra t io n s
Overview
The MAX4554/MAX4555/MAX4556’s construction is typi-
cal of most CMOS analog switches. They have four sup-
ply pins: V+, V-, VL, and GND. V+ and V- are used to
drive the internal CMOS switches and set the analog volt-
age limits on any switch. Reverse ESD protection diodes
are internally connected between each analog and digital
signal pin and both V+ and V-. If any signal exceeds V+
or V-, one of these diodes will conduct. During normal
operation these reverse-biased ESD diodes leak, forming
the only current drawn from the signal paths.
_______________De t a ile d De s c rip t io n
The MAX4554/MAX4555/MAX4556 are CMOS analog
ICs configured as force-sense switches. Each part con-
tains low-resistance switches for forcing current, and
higher resistance switches for sensing a voltage or dri-
ving guard wires. Analog signals on the force, sense, or
guard circuits can range from V- to V+. Each switch is
completely symmetrical and signals are bidirectional;
any switch terminal can be an input or output. The
s witc he s ’ op e n or c los e d s ta te s a re c ontrolle d b y
TTL/CMOS-compatible input (IN_) pins.
Virtually all the analog leakage current comes through
the ESD diodes to V+ or V-. Although the ESD diodes on
a given signal pin are identical, and therefore fairly well
balanced, they are reverse biased differently. Each is
biased by either V+ or V- and the analog signal. This
means their leakages vary as the signal varies. The dif-
ference in the two diode leakages from the signal path
to the V+ and V- pins constitutes the analog-signal-path
leakage current. All analog leakage current flows to the
supply terminals, not to the other switch terminal. This
explains how both sides of a given switch can show
leakage currents of either the same or opposite polarity.
The MAX4555 and MAX4556 are characterized and
guaranteed only with ±15V supplies, but they can oper-
ate from a single supply up to +44V or non-symmetrical
supplies with a voltage totaling less than +44V. The
MAX4554 is fully characterized for operation from ±15V
supplies, and it is also fully specified for operation with
+20V and -10V supplies. A separate logic supply pin,
VL, allows operation with +5V or +3V logic, even with
unusual V+ values. The negative supply pin, V-, must
be connected to GND for single-supply operation.
The re is no c onne c tion b e twe e n the a na log s ig na l
paths and GND or VL. The analog signal paths consist
of a n N-c ha nne l a nd P-c ha nne l MOSFET with the ir
sources and drains paralleled, and their gates driven
out of phase to V+ and V- by the logic-level translators.
The MAX4554 contains two force switches, two sense
switches, and two guard switches configured as two
3PST switches. The two switches operate independent-
ly of one another, but they have a common connection,
allowing one source to be connected simultaneously to
two loads, or two sources to be connected to one load.
An enable pin, EN, turns all switches off when driven to
logic high. The MAX4554 is also fully specified for oper-
ation with +20V and -10V supplies. The MAX4555 con-
tains four independent SPDT, NC switches; two are
forc e s witc he s a nd two a re s e ns e s witc he s . The
MAX4556 contains three independent SPDT switches;
one is a force switch and two are sense switches.
VL and GND power the internal logic and logic-level
translator and set the input logic threshold. The logic-
level translator converts the logic levels to switched V+
a nd V- s ig na ls for d riving the g a te s of the a na log
s witc he s . This d rive s ig na l is the only c onne c tion
between GND and the analog supplies. V+ and V- have
ESD-protection diodes to GND. The logic-level inputs
(IN_, and EN) have ESD protection to V+ and V-, but
not to GND; therefore, the logic signal can go below
GND (as low as V-) when bipolar supplies are used.
The logic-level threshold V is CMOS and TTL compat-
IN
ible when VL is between 4.5V and 36V (see Typical
Operating Characteristics).
______________________________________________________________________________________ 19
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