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MAX4269ESD 参数 Datasheet PDF下载

MAX4269ESD图片预览
型号: MAX4269ESD
PDF下载: 下载PDF文件 查看货源
内容描述: 超低失真,单电源, 300MHz的运算放大器与启用 [Ultra-Low-Distortion, Single-Supply, 300MHz Op Amps with Enable]
分类和应用: 运算放大器放大器电路光电二极管
文件页数/大小: 16 页 / 361 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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Ultra-Low-Distortion, Single-Supply,  
300MHz Op Amps with Enable  
Choosing Resistor Values  
Unity-Gain Configurations  
The MAX4265 and MAX4268 are internally compensat-  
ed for unity gain. When configured for unity gain, they  
require a small resistor (R ) in series with the feedback  
F
path (Figure 1). This resistor improves AC response by  
reducing the Q of the tank circuit, which is formed by  
parasitic feedback inductance and capacitance.  
Driving Capacitive Loads  
The MAX4265–MAX4270 are not designed to drive  
highly reactive loads; stability is maintained with loads  
up to 15pF with less than 2dB peaking in the frequency  
response. To drive higher capacitive loads, place a  
small isolation resistor in series between the amplifier’s  
output and the capacitive load (Figure 1). This resistor  
improves the amplifier’s phase margin by isolating the  
capacitor from the op amp’s output.  
Inverting and Noninverting Configurations  
The values of the gain-setting feedback and input resis-  
tors are important design considerations. Large resistor  
values will increase voltage noise and interact with the  
amplifier’s input and PC board capacitance to generate  
undesirable poles and zeros, which can decrease  
bandwidth or cause oscillations. For example, a nonin-  
To ensure a load capacitance that limits peaking to less  
than 2dB, select a resistance value from Figure 2. For  
example, if the capacitive load is 100pF, the corre-  
sponding isolation resistor is 6(MAX4269). Figures 3  
and 4 show the peaking that occurs in the frequency  
response with and without an isolation resistor.  
Coaxial cable and other transmission lines are easily  
driven when terminated at both ends with their charac-  
teristic impedance. When driving back-terminated  
transmission lines, the capacitive load of the transmis-  
sion line is essentially eliminated.  
verting gain of +2V/V (Figure 1) using R = R = 1kΩ  
F
G
combined with 2pF of input capacitance and 0.5pF of  
board capacitance will cause a feedback pole at  
128MHz. If this pole is within the anticipated amplifier  
bandwidth, it will jeopardize stability. Reducing the 1kΩ  
resistors to 100extends the pole frequency to  
1.28GHz, but could limit output swing by adding 200Ω  
in parallel with the amplifier’s load. Clearly, the selec-  
tion of resistor values must be tailored to the specific  
application.  
ADC Input Buffer  
Input buffer amplifiers can be a source of significant  
errors in high-speed ADC applications. The input buffer  
is usually required to rapidly charge and discharge the  
ADC’s input, which is often capacitive (see Driving  
Capacitive Loads). In addition, since a high-speed  
ADC’s input impedance often changes very rapidly dur-  
ing the conversion cycle, measurement accuracy must  
Distortion Considerations  
The MAX4265–MAX4270 are ultra-low-distortion, high-  
bandwidth op amps. Output distortion will degrade as  
the total load resistance seen by the amplifier decreas-  
es. To minimize distortion, keep the input and gain-set-  
ting resistor values relatively large. A 500feedback  
resistor combined with an appropriate input resistor to  
set the gain will provide excellent AC performance with-  
out significantly increasing distortion.  
R
R
F
G
Noise Considerations  
The amplifier’s input-referred noise-voltage density is  
dominated by flicker noise at lower frequencies and by  
thermal noise at higher frequencies. Because the ther-  
mal noise contribution is affected by the parallel combi-  
nation of the feedback resistive network, those resistor  
values should be reduced in cases where the system  
bandwidth is large and thermal noise is dominant. This  
noise-contribution factor decreases, however, with  
increasing gain settings. For example, the input noise  
voltage density at the op amp input with a gain of  
R *  
S
V
IN  
R
L
C
L
MAX4265  
MAX4266  
MAX4267  
PART  
R
()  
R
()  
G
GAIN (V/V)  
F
MAX4265  
MAX4266  
MAX4267  
24  
500  
125  
1
2
5
500  
500  
+10V/V using R = 100kand R = 11kis e =  
n
F
G
18nV/Hz. The input noise can be reduced to 8nV/Hz  
by choosing R = 1k, R = 110.  
F
G
*OPTIONAL, USED TO MINIMIZE PEAKING FOR C > 15pF.  
L
Figure 1. Noninverting Configuration  
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