S P I/Mic ro w ire -Co m p a t ib le
UART in QS OP -1 6
MAX310
Table 11. Bit Definitions*
Bit
Name
Bit
Name
Register
Bit Set (1)
Bit Clear (0)
Register
Bit Set (1)
Bit Clear (0)
Word length =
7 bits
Word length =
8 bits
Disable FIFO
buffer
Enable FIFO
buffer
Config
L
Config
Config
Config
FEN
SHDNi
TM
Write
Data
Enable normal
operation
Shutdown
Operate
Inhibit TX output
TE
RTS
Pt
Enable transmit-
done interrupt
Disable transmit-
done interrupt
Write
Data
Drive RTS output
pin low
Drive RTS out-
put pin high
Enable data-
received inter-
rupt
Disable data-
received
interrupt
Config
RM
Write
Data
Transmit
parity = 1
Transmit
parity = 0
Enable parity
interrupt
Disable parity
interrupt
Read
Data
Data overrun or
framing error
Config
Config
Config
PM
RAM
IR
RA/FE
CTS
R
Normal
Enable framing-
error interrupt
Disable framing-
error interrupt
Read
Data
CTS input pin is
low
CTS input pin is
high
Enable IrDA
timing mode
Standard
timing
Data has been
received
Data buffer is
empty
All
All
Config
Config
ST
PE
Two stop bits
Parity enabled
One stop bit
Transmit buffer
is empty
UART is busy
transmitting
T
Parity disabled
*Default setting is clear
Table 12. Field Definitions
Table 13. 1.8432MHz Baud Rates
B3...B0
BRD
Baud
B3...B0
BRD
Baud
Register
Field Name
Meaning
0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
115.2k
56k
1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
3
6
38.4k
19.2k
9600
4800
2400
1200
600
Config
B3–B0
D7t–D0t
Pr
Baud-rate divisor
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Write Data
Read Data
Read Data
Transmit data
4
28k
12
24
48
96
192
384
Received parity bit
Received data
8
14k
D7r–D0r
16
32
64
128
7200
3600
1800
900
300
______________________________________________________________________________________ 19
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
