±±15k ESD-Protected, Fail-Safe, High-Speed (±0Mbps),
Slew-Rate-Limited RS-481/RS-422 Transceivers
V
CC
RE
MAX3089E
A
B
RD
TOP VIEW
H/F
RO
1
2
3
4
5
6
7
14
V
CC
RXP
13 RXP
RE
12
11
10
9
A
MAX3089E
DE
B
H/F
Z
DI
Z
TXP
SRL
GND
Y
8
TXP
DIP/SO
Y
DI
NOTE: SWITCH POSITIONS
INDICATED FOR H/F = GND
GND DE
SRL
Figure 4. MAX3089E Pin Configuration and Functional Diagram
Y
1k
TEST POINT
R
RECEIVER
OUTPUT
V
CC
S1
S2
C
RL
V
OD
1k
15pF
R
V
OC
Z
Figure 5. Driver DC Test Load
Figure 6. Receiver Enable/Disable Timing Test Load
The ESD-prꢂceꢁceꢃ ptno are ceoceꢃ wtch referenꢁe cꢂ che
grꢂunꢃ ptn tn a pꢂwereꢃ-ꢃꢂwn ꢁꢂnꢃtctꢂn. They are ceoc-
eꢃ cꢂ ±±15k uotng che Human Bꢂꢃy Mꢂꢃeꢀ.
ꢁhargeꢃ tncꢂ a ꢀꢂw tmpeꢃanꢁe. Thto mꢂꢃeꢀ ꢁꢂnotoco ꢂf
a ±00pF ꢁapaꢁtcꢂr ꢁhargeꢃ cꢂ che ESD vꢂꢀcage ꢂf tncer-
eoc, whtꢁh to chen ꢃtoꢁhargeꢃ tncꢂ che ceoc ꢃevtꢁe
chrꢂugh a ±.15Ω reotocꢂr.
ESD Test Conditions
ESD perfꢂrmanꢁe ꢃepenꢃo ꢂn a vartecy ꢂf ꢁꢂnꢃtctꢂno.
Cꢂncaꢁc Maxtm fꢂr a reꢀtabtꢀtcy repꢂrc chac ꢃꢂꢁumenco
ceoc oecup, ceoc mechꢂꢃꢂꢀꢂgy, anꢃ ceoc reouꢀco.
Machine Model
The Maꢁhtne Mꢂꢃeꢀ fꢂr ESD ceoco aꢀꢀ ptno uotng a
200pF ocꢂrage ꢁapaꢁtcꢂr anꢃ zerꢂ ꢃtoꢁharge reoto-
canꢁe. The ꢂbjeꢁctve to cꢂ emuꢀace che ocreoo ꢁauoeꢃ
when I/O ptno are ꢁꢂncaꢁceꢃ by hanꢃꢀtng equtpmenc
ꢃurtng ceoc anꢃ aooembꢀy. Aꢀꢀ ptno requtre chto prꢂceꢁ-
Human Body Model
Ftgure ±4a ohꢂwo che Human Bꢂꢃy Mꢂꢃeꢀ, anꢃ Ftgure
±4b ohꢂwo che ꢁurrenc wavefꢂrm tc generaceo when ꢃto-
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
