LNAs with Step Attenuator and VGA
Typical Operating Circuits
1.1kΩ
PRECISION
2.775 V
DC
RF_V
GND
CC
RSET
AGC_BYP
MAX2371
MAX2373
LNA_IN
RF
LNA_V
CC
INPUT MATCH
RF
LNA_E
RX_EN
AGC
AMP
LNA
ATTENUATOR
LNA_OUT
EXPONENTIAL
CONVERTER
RF_ATTN
AGC
LNA_I
Impedance-Matching Network Layout
The input- and output-matching networks are sensitive to
layout-related parasitic inductions. To minimize parasitic
inductance, keep traces short and place components as
close as possible to the chip. To minimize parasitic
capacitance, minimize the area of the plane.
Chip Information
TRANSISTOR COUNT: 360
Revision History
Pages changed at Rev 1: 1, 8, 10
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