3A, 1MHz, DDR Memory Termination Supply
MAX1809
V
OUT
= V
EXTREF
LX
V
DDQ
LX
MAX1809
EXTREF
V
OUT
R2
MAX1809
V
EXTREF
(1.1V
≤
V
EXTREF
≤
V
IN
- 1.7V)
EXTREF
FB
FB
R1
R2 = R1[(V
OUT
/ V
EXTREF
) - 1]
Figure 5. Adjusting the Output Voltage Using EXTREF
Figure 6. Adjusting the Output Voltage at FB
The output current limit during soft-start varies with
the voltage on the soft-start pin, SS, according to the
equation:
I
LIM(SS)
=
V
SS
−
0.7V
×
I
LIMIT
1.1V
where I
LIMIT
is the current-limit threshold from the
Electrical Characteristics.
The constant-current source
stops charging once the voltage across the soft-start
capacitor reaches 1.8V.
Applications Information
Frequency Variation with Output Current
The operating frequency of the MAX1809 is determined
primarily by t
OFF
(set by R
TOFF
), V
IN
, and V
OUT
as
shown in the following formula:
f
SW
=
careful component placement, and correct routing of
traces using appropriate trace widths. The following
points are in order of decreasing importance:
1) Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the
output capacitor’s ground, and PGND close together.
Connect the resulting PGND plane to GND at only
one point.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
resistive and switching losses as well as noise.
4) Ground planes are essential for optimum perfor-
mance. In most applications, the circuit is located on
a multilayer board and full use of the four or more
layers is recommended. For heat dissipation, con-
nect the exposed backside pad of the QFN pack-
age to a large analog ground plane, preferably on a
surface of the board that receives good airflow. If
the ground plane is located on the top layer, make
use of the N.C. pins adjacent to GND to lower thermal
resistance to the ground plane. If the ground is
located elsewhere, use several vias to lower thermal
resistance. Typical applications use multiple ground
planes to minimize thermal resistance. Avoid large
AC currents through the analog ground plane.
(
V
IN
−
V
OUT
−
V
PMOS
)
t
OFF
(
V
IN
−
V
PMOS
+
V
NMOS
)
However, as the output current increases, the voltage
drop across the NMOS and PMOS switches increases
and the voltage across the inductor decreases. This
causes the frequency to drop. Assuming R
PMOS
=
R
NMOS
, the change in frequency can be approximated
with the following formula:
∆
f
SW
=
∆
I
OUT
×
R
PMOS
(
V
IN
×
t
OFF
)
Voltage Positioning
In applications where the load transients are extremely
fast (>10A/µs), the total output capacitance has to be
large enough to handle the V
SAG
and V
SOAR
require-
ments while keeping within the output tolerance limits.
Voltage positioning reduces the total amount of output
capacitance needed to meet a given transient
response requirement. With voltage positioning, the
11
where R
PMOS
is the resistance of the internal MOSFETs
(90mΩ typ).
Circuit Layout and Grounding
Good layout is necessary to achieve the MAX1809’s
intended output power level, high efficiency, and low
noise. Good layout includes the use of ground planes,
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