Low-Cost, Multichemistry Battery-
Charger Building Block
ꢃBSꢀLꢄTE MꢃXIMꢄM RꢃTINGS
DCIN, CSSP, CSSN to GND...................................-0.3V to +30V
BST to GND............................................................-0.3V to +36V
BST to LX..................................................................-0.3V to +6V
DLO to PGND .........................................-0.3V to (V
LDO Short-Circuit Current ..................................................50mA
+ 0.3V)
DLOV
Continuous Power Dissipation (T = +70°C)
A
DHI to LX...................................................-0.3V to (V
+ 0.3V)
28-Pin QSOP (derate 12.6mW/°C above +70°C).......1008mW
BST
LX to GND .................................................................-6V to +30V
BATT, CSIP, CSIN to GND........................................-0.3V to 20V
CSIP to CSIN or CSSP to CSSN or
PGND to GND ...........……….……………..…….-0.3V to +0.3V
CCI, CCS, CCV, DLO, ICHG, IINP,
Junction-to-Ambient Thermal Resistance (θ )
JA
(Note 1) .....................................................................79.3°C/W
Junction-to-Case Thermal Resistance ( θ
)
JC
(Note 1) ........................................................................27°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ........................................................150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
MAX172
ACIN, REF to GND ...............................-0.3V to (V
DLOV, VCTL, ICTL, REFIN, CELLS,
+ 0.3V)
LDO
CLS, LDO, ACOK to GND ....................................-0.3V to +6V
DLOV to LDO.........................................................-0.3V to +0.3V
NVte 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www0mꢂxim-iA0AVm/thermꢂo-tutVriꢂo.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICꢃL CHꢃRꢃCTERISTICS
ꢀ
(V
= V
= V
= 18V, V
= V
= V
= V
= 12V, V
= 3.0V, V
= 1µF, LDO = DLOV, C
= V
= 0.75
REF
V
, V
= 2.0V,
CELLS
DCIN
CSSP
CSSN
BATT
- V = 4.5V, V
CSIP
CSIN
REFIN
VCTL
ICTL
REFIN
V
= 0V, CLS = REF, V
= 0V, C
= 1µF; pins CCI, CCS, and CCV
ACIN
BST
LX
GND
PGND
LDO
are compensated per Figure 1a; T = ±°C tV +8.°C, unless otherwise noted. Typical values are at T = +25°C.)
ꢃ
A
PꢃRꢃMETER
SYMBꢀL
CꢀNDITIꢀNS
MIN
TYP
MꢃX
ꢄNITS
SꢄPPLY ꢃND LDꢀ REGꢄLꢃTꢀR
V
DCIN Input Voltage Range
8
28
V
V
DCIN
V
V
falling
rising
7.0
7.4
7.5
2.7
5.40
34
DCIN
DCIN
DCIN Undervoltage Lockout
Trip Point
7.85
6.0
I
8.0V < V
8.0V < V
< 28V
DCIN Quiescent Current
LDO Output Voltage
LDO Load Regulation
mA
V
DCIN
DCIN
DCIN
< 28V, no load
5.25
5.55
100
0 < I
LDO
< 10mA
mV
LDO Undervoltage Lockout
Trip Point
V
= 8.0V
3.20
4.00
4.096
3.1
5.15
4.120
3.9
V
V
V
DCIN
0 < I
V
< 500µA
REF Output Voltage
4.072
REF
REF Undervoltage Lockout
Trip Point
falling
REF
TRIP PꢀINTS
V
falling
BATT POWER_FAIL Threshold
50
100
200
150
300
mV
mV
CSSP
BATT POWER_FAIL Threshold
Hysteresis
100
V
rising
ACIN Threshold
2.007
10
2.048
20
2.089
30
V
mV
µA
V
ACIN
0.5% of V
ACIN Threshold Hysteresis
ACIN Input Bias Current
CLS Input Range
REF
V
V
V
= 2.048V
-1
+1
ACIN
1.6
-1
REF
+1
= 2.0V
=16.8V
CLS Input Bias Current
µA
CLS
SWITCHING REGꢄLꢃTꢀR
Minimum Off-Time
1.00
1.25
1.50
µs
BATT
2
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
