Stand-Alone, Switch-Mode
Li+ Battery Charger with Internal 28V Switch
MAX1758
Pin Description
PIN
1
2
3
4
5
6
7
8
9, 10
11
12
13
14
15
16
17
18
19, 20
21
22
23
24
25
26
27
28
NAME
VL
ISETIN
ISETOUT
THM
REF
GND
VADJ
BATT
HSD
CELL
TIMER1
TIMER2
FAULT
FASTCHG
FULLCHG
SHDN
PGND
LX
CS
BST
CCS
CCI
CCV
CSSN
CSSP
DCIN
FUNCTION
Chip Power Supply. Output of the 5.4V linear regulator from DCIN. Bypass VL to GND with 2.2µF or larger
ceramic capacitor.
Input Current Limit Adjust. Use a voltage-divider to set the voltage between 0 and V
REF
. See
Input Current
Regulator
section.
Battery Charging Current Adjust. Use a voltage-divider to set the voltage between 0 and V
REF
. See
Charging Current Regulator
section.
Thermistor Input. Connect a thermistor from THM to GND to set qualification temperature range. If unused,
connect a 10kΩ resistor from THM to GND. See
Thermistor
section.
4.2V Reference Voltage Output. Bypass REF to GND with 1µF or larger ceramic capacitor.
Analog Ground
Voltage Adjustment. Use a voltage-divider to set the voltage between 0 and V
REF
to adjust the battery reg-
ulation voltage by ±5%. See
Battery Regulation Voltage
section.
Battery Voltage-Sense Input and Current-Sense Negative Input
High-Side Drain. This is the drain of the internal high-side FET. See Figure 3.
Cell-Count Programming Input. Connect CELL to GND, REF, or VL to set 1, 3, or 4 cells, or leave uncon-
nected to set 2 cells.
Timer1 Adjustment. Connect a capacitor from TIMER1 to GND to set the prequalification, full-charge, and
top-off times. See
Timers
section.
Timer2 Adjustment. Connect a capacitor from TIMER2 to GND to set the fast-charge time. See
Timers
section.
Charge Fault Indicator. Open-drain output pulls low when charging terminates abnormally. See Table 1.
Fast-Charge Indicator. Open-drain output pulls low when charging with constant current.
Full-Charge Indicator. Open-drain output pulls low when charging with constant voltage in full-charge
state.
Shutdown Input. Drive
SHDN
low to disable charging. Connect
SHDN
to VL for normal operation.
Power Ground. Current from the low-side power MOSFET switch source flows through PGND.
Power Inductor Switching Node and High-Side Power MOSFET Source
Battery Current-Sense Positive Input. Connects to internal 0.1Ω resistor between BATT and CS.
High-Side MOSFET Gate Drive Bias. Connect a 0.1µF capacitor from BST to LX.
Charger Source Current Regulation Loop Compensation Point. See
Compensation
section.
Battery Charge Current Regulation Loop Compensation Point. See
Compensation
section.
Voltage Regulation Loop Compensation Point. See
Compensation
section.
Source Current-Sense Negative Input. See
Input Current Regulator
section.
Source Current-Sense Positive Input. See
Input Current Regulator
section.
Power-Supply Input. DCIN is the input supply for the VL regulator. Bypass DCIN to GND with a 0.1µF or
greater capacitor. See
Detailed Description.
8
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