Multi-Output, Low-Noise Power-Supply
Controllers for Notebook Computers
MAX1630–MAX1635
_________________________________________________Pin Description (continued)
PIN
NAME
V
DD
(MAX1630/
32/33/35)
5
SECFB
(MAX1631/
MAX1634)
6
7
8
9
10
11
SYNC
TIME/ON5
GND
REF
SKIP
RESET
Secondary Winding Feedback Input. Normally connected to a resistor divider from an auxiliary output.
SECFB regulates at V
SECFB
= 2.5V (see
Secondary Feedback Regulation Loop
section). Tie to VL if not
used.
Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz
operation. Can be driven at 240kHz to 350kHz for external synchronization.
Dual-Purpose Timing Capacitor Pin and ON/OFF Control Input. See
Power-Up Sequencing and
ON/
OFF
Controls
section.
Low-Noise Analog Ground and Feedback Reference Point
2.5V Reference Voltage Output. Bypass to GND with 1µF minimum.
Logic-Control Input that disables Idle Mode when high. Connect to GND for normal use.
Active-Low Timed Reset Output.
RESET
swings GND to VL. Goes high after a fixed 32,000 clock-cycle
delay following power-up.
Feedback Input for the 5V SMPS; regulates at FB5 = REF (approx. 2.5V) in adjustable mode. FB5 is a
Dual Mode input that also selects the 5V fixed output voltage setting when tied to GND. Connect FB5 to
a resistor divider for adjustable-output mode.
Current-Sense Input for the 5V SMPS. Also serves as the feedback input in fixed-output mode, and as
the bootstrap supply input when the voltage on CSL5/VL is > 4.5V.
Current-Sense Input for the 5V SMPS. Current-limit level is 100mV referred to CSL5.
Pin-Strap Input that selects the SMPS power-up sequence:
SEQ = GND: 5V before 3.3V,
RESET
output determined by both outputs
SEQ = REF: Separate ON3/ON5 controls,
RESET
output determined by 3.3V output
SEQ = VL: 3.3V before 5V,
RESET
output determined by both outputs
Gate-Drive Output for the 5V, high-side N-channel switch. DH5 is a floating driver output that swings
from LX5 to BST5, riding on the LX5 switching node voltage.
Switching Node (inductor) Connection. Can swing 2V below ground without hazard.
Boost capacitor connection for high-side gate drive (0.1µF)
Gate-Drive Output for the low-side synchronous-rectifier MOSFET. Swings 0V to VL.
Power Ground
5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. After the 5V SMPS
output has reached +4.5V (typical), VL automatically switches to the output voltage via CSL5 for boot-
strapping. Bypass to GND with 4.7µF. VL supplies up to 25mA for external loads.
Battery Voltage Input, +4.2V to +30V. Bypass V+ to PGND close to the IC with a 0.22µF capacitor.
Connects to a linear regulator that powers VL.
Shutdown Control Input, active low. Logic threshold is set at approximately 1V. For automatic start-up,
connect
SHDN
to V+ through a 220kΩ resistor and bypass
SHDN
to GND with a 0.01µF capacitor.
Gate-Drive Output for the low-side synchronous-rectifier MOSFET. Swings 0V to VL.
Boost Capacitor Connection for high-side gate drive (0.1µF)
Switching Node (inductor) Connection. Can swing 2V below ground without hazard.
Gate-Drive Output for the 3.3V, high-side N-channel switch. DH3 is a floating driver output that swings
from LX3 to BST3, riding on the LX3 switching node voltage.
ON/OFF Control Input. See
Power-Up Sequencing and ON/
OFF
Controls
section.
FUNCTION
Supply Voltage Input for the 12OUT Linear Regulator. Also connects to an internal resistor divider for
secondary winding feedback, and to an 18V overvoltage shunt regulator clamp.
12
13
14
15
FB5
CSL5
CSH5
SEQ
16
17
18
19
20
21
22
23
24
25
26
27
28
DH5
LX5
BST5
DL5
PGND
VL
V+
SHDN
DL3
BST3
LX3
DH3
RUN/ON3
_______________________________________________________________________________________
7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
