Hig h -Effic ie n c y, P WM, S t e p -Do w n
DC-DC Co n t ro lle rs in 1 6 -P in QS OP
The MAX1652–MAX1655 c onta in nine ma jor c irc uit
blocks, which are shown in Figure 2:
charge losses. The oscillator is effectively gated off at
light loads because the Idle Mode comparator immedi-
ately resets the high-side latch at the beginning of each
cycle, unless the feedback signal falls below the refer-
ence voltage level.
PWM Controller Blocks:
• Multi-Input PWM Comparator
• Current-Sense Circuit
When in PWM mode, the controller operates as a fixed-
frequency current-mode controller where the duty ratio
is set by the input/output voltage ratio. The current-
mode feedback system regulates the peak inductor
current as a function of the output voltage error signal.
Since the average inductor current is nearly the same
as the peak current, the circuit acts as a switch-mode
transconductance amplifier and pushes the second out-
p ut LC filte r p ole , norma lly found in a d uty-fa c tor-
controlled (voltage-mode) PWM, to a higher frequency.
To preserve inner-loop stability and eliminate regenera-
tive inductor current “staircasing,” a slope-compensa-
tion ramp is summed into the main PWM comparator to
reduce the apparent duty factor to less than 50%.
• PWM Logic Block
• Dual-Mode Internal Feedback Mux
• Gate-Driver Outputs
• Secondary Feedback Comparator
Bias Generator Blocks:
• +5V Linear Regulator
• Automatic Bootstrap Switchover Circuit
• +2.50V Reference
These internal IC blocks aren’t powered directly from
the battery. Instead, a +5V linear regulator steps down
the battery voltage to supply both the IC internal rail (VL
pin) a s we ll a s the ga te d rive rs. The sync hronous-
switch gate driver is directly powered from +5V VL,
while the high-side-switch gate driver is indirectly pow-
ered from VL via an external diode-capacitor boost cir-
cuit. An automatic bootstrap circuit turns off the +5V
linear regulator and powers the IC from its output volt-
age if the output is above 4.5V.
2–MAX165
The relative gains of the voltage- and current-sense
inputs are weighted by the values of current sources
that bias three differential input stages in the main PWM
comparator (Figure 4). The relative gain of the voltage
comparator to the current comparator is internally fixed
at K = 2:1. The resulting loop gain (which is relatively
low) determines the 2% typical load regulation error.
The low loop -g a in va lue he lp s re d uc e outp ut filte r
c a p a c itor s ize a nd c os t b y s hifting the unity-g a in
crossover to a lower frequency.
P WM Co n t ro lle r Blo c k
The he a rt of the c urre nt-mod e PWM c ontrolle r is a
multi-input open-loop comparator that sums three sig-
nals: output voltage error signal with respect to the ref-
e re nc e volta g e , c urre nt-s e ns e s ig na l, a nd s lop e
compensation ramp (Figure 3). The PWM controller is a
direct summing type, lacking a traditional error amplifi-
er and the phase shift associated with it. This direct-
s umming c onfig ura tion a p p roa c he s the id e a l of
cycle-by-cycle control over the output voltage.
The output filter capacitor C2 sets a dominant pole in
the feedback loop. This pole must roll off the loop gain
to unity b e fore the ze ro introd uc e d b y the outp ut
capacitor’s parasitic resistance (ESR) is encountered
(see Design Procedure section). A 12kHz pole-zero
cancellation filter provides additional rolloff above the
unity-gain crossover. This internal 12kHz lowpass com-
pensation filter cancels the zero due to the filter capaci-
tor’s ESR. The 12kHz filter is included in the loop in
both fixed- and adjustable-output modes.
Under heavy loads, the controller operates in full PWM
mode. Each pulse from the oscillator sets the main
PWM latch that turns on the high-side switch for a peri-
od d e te rmine d b y the d uty fa c tor (a p p roxima te ly
V
/V ). As the high-side switch turns off, the syn-
OUT IN
chronous rectifier latch is set. 60ns later the low-side
switch turns on, and stays on until the beginning of the
ne xt c loc k c yc le (in c ontinuous mod e ) or until the
inductor current crosses zero (in discontinuous mode).
Und e r fa ult c ond itions whe re the ind uc tor c urre nt
exceeds the 100mV current-limit threshold, the high-
side latch resets and the high-side switch turns off.
S yn c h ro n o u s -Re c t ifie r Drive r (DL P in )
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky diode with
a low-resistance MOSFET switch. The synchronous rec-
tifier also ensures proper start-up of the boost-gate driv-
e r c irc uit. If you mus t omit the s ync hronous p owe r
MOSFET for cost or other reasons, replace it with a
small-signal MOSFET such as a 2N7002.
If the load is light in Idle Mode (SKIP = low), the induc-
tor current does not exceed the 25mV threshold set by
the Idle Mode comparator. When this occurs, the con-
troller skips most of the oscillator pulses in order to
reduce the switching frequency and cut back gate-
If the circuit is operating in continuous-conduction mode,
the DL drive waveform is simply the complement of the
DH high-side drive waveform (with controlled dead
time to prevent cross-conduction or “shoot-through”).
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
