Mu lt i-Ou t p u t , Lo w -No is e P o w e r-S u p p ly
Co n t ro lle rs fo r No t e b o o k Co m p u t e rs
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, T = T
to T , unless otherwise noted.
MAX
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT DETECTION (MAX1630/MAX1631/MAX1632)
Overvoltage Trip Threshold
Overvoltage-Fault Propagation Delay
Output Undervoltage Threshold
Output Undervoltage Lockout Time
Thermal Shutdown Threshold
RESET
With respect to unloaded output voltage
CSL_ driven 2% above overvoltage trip threshold
With respect to unloaded output voltage
4
7
10
%
µs
1.5
60
70
80
%
From each SMPS enabled, with respect to f
Typical hysteresis = +10°C
5000
6144
150
7000
clks
°C
OSC
With respect to unloaded output voltage,
falling edge; typical hysteresis = 1%
-7
-5.5
1.5
-4
%
RESET Trip Threshold
Falling edge, CSL_ driven 2%
below RESET trip threshold
µs
RESET Propagation Delay
With respect to f
OSC
27,000 32,000 37,000
clks
RESET Delay Time
0–MAX1635
INPUTS AND OUTPUTS
Feedback Input Leakage Current
FB3, FB5; SECFB = 2.6V
1
50
nA
V
RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC
Logic Input Low Voltage
Logic Input High Voltage
0.6
RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
SHDN, STEER, SYNC
2.4
V
RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),
Input Leakage Current
±1
µA
V
SHDN, STEER, SYNC, SEQ; V
= 0V or 3.3V
PIN
Logic Output Low Voltage
0.4
RESET, I
= 4mA
SINK
Logic Output High Current
TIME/ON5 Input Trip Level
TIME/ON5 Source Current
TIME/ON5 On-Resistance
Gate Driver Sink/Source Current
Gate Driver On-Resistance
1
mA
V
RESET = 3.5V
SEQ = 0V or VL
2.4
2.5
2.6
3.5
80
TIME/ON5 = 0V, SEQ = 0V or VL
3
15
1
µA
Ω
TIME/ON5; RUN/ON3 = 0V, SEQ = 0V or VL
DL3, DH3, DL5, DH5; forced to 2V
High or low
A
1.5
7
Ω
Note 1: Each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mV increments.
Note 2: High duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating
frequency (see Overload and Dropout Operation section).
Note 3: MAX1630/MAX1632/MAX1633/MAX1635 only.
Note 4: Off mode for the 12V linear regulator occurs when the SMPS that has flyback feedback (V ) steered to it is disabled. In
DD
situations where the main outputs are being held up by external keep-alive supplies, turning off the 12OUT regulator pre-
vents a leakage path from the output-referred flyback winding, through the rectifier, and into V
.
DD
Note 5: Since the reference uses VL as its supply, the reference’s V+ line-regulation error is insignificant.
4
_______________________________________________________________________________________