Mu lt i-Ou t p u t , Lo w -No is e P o w e r-S u p p ly
Co n t ro lle rs fo r No t e b o o k Co m p u t e rs
under all operating conditions, including Idle Mode.
The SECFB signal further controls the synchronous
switch timing in order to improve multiple-output cross-
regulation (see Secondary Feedback Regulation Loop
section).
turns on the high-side MOSFET by closing an internal
switch between BST_ and DH_. This provides the nec-
essary enhancement voltage to turn on the high-side
switch, an action that “boosts” the 5V gate-drive signal
above the battery voltage.
Ringing at the high-side MOSFET gate (DH3 and DH5)
in discontinuous-conduction mode (light loads) is a nat-
ural operating condition. It is caused by residual ener-
gy in the tank circuit, formed by the inductor and stray
capacitance at the switching node, LX. The gate-drive
negative rail is referred to LX, so any ringing there is
directly coupled to the gate-drive output.
In t e rn a l VL a n d REF S u p p lie s
An internal regulator produces the +5V supply (VL) that
powers the PWM controller, logic, reference, and other
blocks within the IC. This 5V low-dropout linear regula-
tor s up p lie s up to 25mA for e xte rna l loa d s , with a
re s e rve of 25mA for s up p lying g a te -d rive p owe r.
Bypass VL to GND with 4.7µF.
Important: Ens ure tha t VL d oe s not e xc e e d 6V.
Measure VL with the main output fully loaded. If it is
p ump e d a b ove 5.5V, e ithe r e xc e s s ive b oos t d iod e
capacitance or excessive ripple at V+ is the probable
cause. Use only small-signal diodes for the boost cir-
c uit (10mA to 100mA Sc hottky or 1N4148 a re p re-
ferred), and bypass V+ to PGND with 4.7µF directly at
the package pins.
Cu rre n t -Lim it in g a n d Cu rre n t -S e n s e
In p u t s (CS H a n d CS L)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor (R1) must be sized for
0–MAX1635
The 2.5V reference (REF) is accurate to ±2% over tem-
perature, making REF useful as a precision system ref-
erence. Bypass REF to GND with 1µF minimum. REF
can supply up to 5mA for external loads. (Bypass REF
with a minimum 1µF/mA re fe re nc e loa d c urre nt.)
However, if extremely accurate specifications for both
the main output voltages and REF are essential, avoid
loading REF more than 100µA. Loading REF reduces
the main output voltage slightly, because of the refer-
ence load-regulation error.
80mV/I
, where I
is the required peak inductor
PEAK
PEAK
current to support the full load current, while compo-
nents must be designed to withstand continuous cur-
rent stresses of 120mV/R1.
For breadboarding or for very-high-current applications,
it may be useful to wire the current-sense inputs with a
twisted pair, rather than PC traces. (This twisted pair
needn’t be anything special; two pieces of wire-wrap
wire twisted together are sufficient.) This reduces the
possible noise picked up at CSH_ and CSL_, which can
cause unstable switching and reduced output current.
When the 5V main output voltage is above 4.5V, an
internal P-channel MOSFET switch connects CSL5 to
VL, while simultaneously shutting down the VL linear
regulator. This action bootstraps the IC, powering the
internal circuitry from the output voltage, rather than
The CSL5 input also serves as the IC’s bootstrap sup-
ply input. Whenever V
> 4.5V, an internal switch
CSL5
connects CSL5 to VL.
throug h
a line a r re g ula tor from the b a tte ry.
Os c illa t o r Fre q u e n c y a n d
S yn c h ro n iza t io n (S YNC)
Bootstrapping reduces power dissipation due to gate
charge and quiescent losses by providing that power
from a 90%-efficient switch-mode source, rather than
from a much less efficient linear regulator.
The SYNC input controls the oscillator frequency. Low
selects 200kHz; high selects 300kHz. SYNC can also
be used to synchronize with an external 5V CMOS or
TTL clock generator. SYNC has a guaranteed 240kHz
to 350kHz capture range. A high-to-low transition on
SYNC initiates a new cycle.
Bo o s t Hig h -S id e Ga t e -Drive S u p p ly
(BS T3 a n d BS T5 )
Gate-drive voltage for the high-side N-channel switches
is g e ne ra te d b y a flying -c a p a c itor b oos t c irc uit
(Figure 2). The capacitor between BST_ and LX_ is
alternately charged from the VL supply and placed par-
allel to the high-side MOSFET’s gate-source terminals.
300kHz operation optimizes the application circuit for
component size and cost. 200kHz operation provides
inc re a s e d e ffic ie nc y, lowe r d rop out, a nd imp rove d
load-transient response at low input-output voltage dif-
ferences (see Low-Voltage Operation section).
On s ta rt-up , the s ync hronous re c tifie r (low-s id e
MOSFET) forc e s LX_ to 0V a nd c ha rg e s the b oos t
capacitors to 5V. On the second half-cycle, the SMPS
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
