Re m o t e /Lo c a l Te m p e ra t u re S e n s o r
w it h S MBu s S e ria l In t e rfa c e
Table 8. RLTS and RRTE Temp Register Update Timing Chart
7
NEW CONVERSION RATE
(CHANGED VIA WRITE TO
WCRW)
TIME UNTIL RLTS AND RRTE
ARE UPDATED
OPERATING MODE
CONVERSION INITIATED BY:
Auto-Convert
Auto-Convert
Power-on reset
n/a (0.25Hz)
n/a
156ms max
156ms max
1-shot command, while idling
between automatic conversions
MAX61
1-shot command that occurs
during a conversion
When current conversion is
complete (1-shot is ignored)
Auto-Convert
n/a
Auto-Convert
Rate timer
Rate timer
Rate timer
Rate timer
Rate timer
Rate timer
Rate timer
Rate timer
STBY pin
0.0625Hz
0.125Hz
0.25Hz
0.5Hz
1Hz
20sec
Auto-Convert
10sec
Auto-Convert
5sec
Auto-Convert
2.5sec
1.25sec
625ms
312.5ms
237.5ms
156ms
156ms
156ms
Auto-Convert
Auto-Convert
2Hz
Auto-Convert
4Hz
Auto-Convert
8Hz
Hardware Standby
Software Standby
Software Standby
n/a
RUN/STOP bit
1-shot command
n/a
n/a
S la ve Ad d re s s e s
Table 9. Slave Address Decoding (ADD0
and ADD1)
The MAX1617 appears to the SMBus as one device
having a common address for both ADC channels. The
device address can be set to one of nine different val-
ues by pin-strapping ADD0 and ADD1 so that more
than one MAX1617 can reside on the same bus without
address conflicts (Table 9).
ADD0
GND
ADD1
GND
ADDRESS
0011 000
0011 001
0011 010
0101 001
0101 010
0101 011
1001 100
1001 101
1001 110
GND
High-Z
GND
V
CC
The address pin states are checked at POR only, and
the address data stays latched to reduce quiescent
supply current due to the bias current needed for high-Z
state detection.
High-Z
High-Z
High-Z
GND
High-Z
V
CC
V
CC
GND
The MAX1617 a ls o re s p ond s to the SMBus Ale rt
Re s p ons e s la ve a d d re s s (s e e the Ale rt Re s p ons e
Address section).
V
CC
High-Z
V
CC
V
CC
P OR a n d UVLO
The MAX1617 has a volatile memory. To prevent ambigu-
ous power-supply conditions from corrupting the data in
memory and causing erratic behavior, a POR voltage
Note: High-Z means that the pin is left unconnected and floating.
Power-Up Defaults:
•
•
•
•
Interrupt latch is cleared.
detector monitors V and clears the memory if V falls
CC
CC
below 1.7V (typical, see Electrical Characteristics table).
Address select pins are sampled.
ADC begins auto-converting at a 0.25Hz rate.
When power is first applied and V rises above 1.75V
CC
(typical), the logic blocks begin operating, although reads
Comma nd b yte is s e t to 00h to fa c ilita te q uic k
remote Receive Byte queries.
and writes at V levels below 3V are not recommended.
CC
A second V comparator, the ADC UVLO comparator,
CC
prevents the ADC from converting until there is sufficient
•
T
and T
registers are set to max and min
HIGH
LOW
headroom (V = 2.8V typical).
CC
limits, respectively.
14 ______________________________________________________________________________________
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
