28V Internal Switch LCD Bias Supply
with True Shutdown
L1
10µH
D1, D2 = CENTRAL SEMICONDUCTOR
CMPD7000 (DUAL)
D3 = CENTRAL SEMICONDUCTOR
CMSD4448 (1N4148)
SW
D3
V
V
= 0.8V TO 5.5V
IN
LX
FB
BATT
C5
10µF
C4
0.01µF
R1
R3
1Ω
C1
1nF
240k R2
MAX1606
16.5k
= 2.4V TO 5.5V
CC
V
CC
C1
C6
0.1µF
1µF
V
= -19V
LIM
NEG
D2
C2
1µF
ON
D1
SHDN
GND
OFF
Figure 4. Negative Voltage for LCD Bias
switching current. Choose a reverse breakdown voltage
greater than the output voltage.
In particular, external feedback resistors should be as
close to FB as possible. To minimize output voltage rip-
ple, and to maximize output power and efficiency, use a
ground plane and solder GND directly to the ground
plane. Refer to the MAX1606EVKIT evaluation kit for a
layout example.
Capacitors
For most applications, use a small 1µF ceramic sur-
face-mount output capacitor. For small ceramic capaci-
tors, the output ripple voltage is dominated by the
capacitance value. If tantalum or electrolytic capacitors
are used, the higher ESR increases the output ripple
voltage. Decreasing the ESR reduces the output ripple
voltage and the peak-to-peak transient voltage.
Surface-mount capacitors are generally preferred
because they lack the inductance and resistance of
their through-hole equivalents.
Applications Information
Negative Voltage for LCD Bias
The MAX1606 can also generate a negative output by
adding a diode-capacitor charge-pump circuit (D1, D2,
and C3) to the LX pin as shown in Figure 4. Feedback
is still connected to the positive output, which is not
loaded, allowing a very small capacitor value at C4. For
best stability and lowest ripple, the time constant of the
R1-R2 series combination and C4 should be near or
less than that of C2 and the effective load resistance.
Output load regulation of the negative output is some-
what looser than with the standard positive output cir-
cuit, and may rise at very light loads due to coupling
through the capacitance of D2. If this is objectionable,
reduce the resistance of R1 and R2, while maintaining
their ratio, to effectively preload the output with a few
hundred microamps. This is why the R1-R2 values
shown in Figure 4 are about four-times lower than typi-
cal values used for a positive-output design. When
loaded, the negative output voltage will be slightly
lower (closer to ground by approximately a diode for-
ward voltage) than the inverse of the voltage on C4.
Two inputs, V
and V
, require bypass capacitors.
BATT
CC
Bypass V
with a 1µF ceramic capacitor as close to
CC
the IC as possible. The BATT input supplies high cur-
rents to the inductor and requires local bulk bypassing
close to the inductor. A 10µF low-ESR surface-mount
capacitor is sufficient for most applications.
A feed-forward capacitor connected from the output to
FB improves stability over a wide range of battery volt-
ages. A 10pF capacitor is sufficient for most applica-
tions. Larger values (up to 47pF) may be needed with
lower current-limit settings (LIM = GND or open) and
low input voltages, or with nonoptimum PC board lay-
outs. Note that increasing C may slightly affect load
FF
regulation.
PC Board Layout and Grounding
Careful printed circuit layout is important for minimizing
ground bounce and noise. Keep the MAX1606’s
ground pin and the ground leads of the input and out-
put capacitors less than 0.2in (5mm) apart. In addition,
keep all connections to FB and LX as short as possible.
Chip Information
TRANSISTOR COUNT: 3883
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