MAX153
1Msps, µP-Compatible,
8-Bit ADC with 1µA Power-Down
TIMING CHARACTERISTICS (Note 5) (continued)
(V
DD
= +5V ±5%, V
SS
= 0V for Unipolar Input Range, V
SS
= -5V ±5% for Bipolar Input Range, 100% production tested, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
WR
to
INT
Delay
(Pipelined Mode)
SYMBOL
t
IHWR
C
L
= 50pF
T
A
= T
MIN
to T
MAX
, C
L
= 50pF
C
L
= 20pF
Data-Access Time After
INT (Note 2)
t
ID
T
A
= T
MIN
to T
MAX
, C
L
= 20pF
C
L
= 100pF
T
A
= T
MIN
to T
MAX
, C
L
= 100pF
CONDITIONS
MIN
TYP
MAX
80
100
30
35
45
60
ns
UNITS
ns
Note 5:
Input control signals are specified with t
r
= t
t
= 5ns, 10% to 90% of +5V and timed from a 1.6V voltage level.
Note 6:
R
L
= 5.1kΩ pullup resistor.
Note 7:
See Figure 2 for load circuit. Parameter defined as the time required for data lines to change 0.5V.
+5V
3kΩ
DN
3kΩ
DGND
A. HIGH-Z TO V
OH
B. HIGH-Z TO V
OL
C
L
DN
C
L
DGND
DN
3kΩ
DGND
A. V
OH
TO HIGH-Z
10pF
DN
+5V
3kΩ
10pF
DGND
B. V
OL
TO HIGH-Z
Figure 1. Load Circuits for Data-Access Time Test
Figure 2. Load Circuits for Data-Hold Time Test
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