±18-Bit ADC with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, R
INT
= 602kΩ, C
INT
= 0.0047µF, C
REF
= 0.1µF,
f
CLK
= 32,768Hz, 60Hz mode, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
DIGITAL SECTION
DOUT, I
OUT
= -1mA
Output High
V
OH
DOUT, I
OUT
= -100µA
EOC, P0–P3, I
OUT
= -100µA
Output Low
Input High
Input Low
Input Current
Input Capacitance
V
OL
V
IH
V
IL
I
IN
C
IN
DOUT, I
OUT
= 1.6mA
EOC, P0–P3, I
OUT
= 100µA
Referred to DGND, 4.5V
≤
V+
≤
5.5V, CS, DIN, SCLK
Referred to DGND, 4.5V
≤
V+
≤
5.5V, CS, DIN, SCLK
CS, DIN, SCLK, and DOUT when three-stated
CS, DIN, SCLK, and DOUT when three-stated
±10
2.4
0.8
±500
5
3.5
4.0
4.0
4.3
4.5
4.7
0.1
0.1
0.4
0.4
V
V
V
nA
pF
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX132
INTERFACE TIMING
(Test Circuit of Figure 1, Figure 2, V+ = 5V, V- = -5V, DGND = AGND = 0V, T
A
= +25°C, unless otherwise noted.) (Note 3)
PARAMETER
CS Lead Time
CS Lag Time
S
CLK
High Time
S
CLK
Low Time
CS High Pulse Width
DIN to SCLK Setup Time
DIN to SCLK Hold Time
DOUT Access Time from Three-State
Data Valid
DOUT Disable Time to Three-State
Delay to P0–P3 High
Delay to P0–P3 Low
Note 1:
Note 2:
Note 3:
Note 4:
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
See Figure 4
230
230
See Figure 3
CONDITIONS
MIN
500
400
400
300
1
0
200
320
60
320
350
350
TYP
MAX
UNITS
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
±18-bit accuracy achieved by averaging multiple conversions.
Maximum deviation from best straight-line fit.
Guaranteed by design, not tested.
Difference in reading for equal positive and negative inputs near full scale.
_______________________________________________________________________________________
3
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
