+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
MAX1248/MAX1249
Table 4. Typical Power-Up Delay Times
REFERENCE
BUFFER
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
REFERENCE-BUFFER
COMPENSATION
MODE
Internal
Internal
External
External
—
—
VREF
CAPACITOR
(µF)
—
—
4.7
4.7
—
—
POWER-DOWN
MODE
Fast
Full
Fast
Full
Fast
Full
POWER-UP
DELAY
(µs)
5
300
See Figure 13c
See Figure 13c
2
2
MAXIMUM
SAMPLING RATE
(ksps)
26
26
133
133
133
133
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
EXTERNAL
EXTERNAL
SETS SOFTWARE
POWER-DOWN
SX X XX X 0 0
SETS EXTERNAL
CLOCK MODE
S XX XXX 1 1
DOUT
10+2 DATA BITS
10+2 DATA BITS
VALID
DATA
INVALID
DATA
HARDWARE
POWER-
DOWN
MODE
POWERED UP
SOFTWARE
POWER-DOWN
POWERED UP
POWERED UP
Figure 11a. Timing Diagram Power-Down Modes, External Clock
CLOCK
MODE
INTERNAL
SETS INTERNAL
CLOCK MODE
S X X X X X 1 0
SX X XX X 0 0
SETS
POWER-DOWN
S
DIN
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
POWERED UP
CONVERSION
POWER-DOWN
POWERED UP
Figure 11b. Timing Diagram Power-Down Modes, Internal Clock
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15
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
