MAX1232
Microprocessor Monitor
AC Electrical Characteristics
(V
CC
= +5V ±10%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
PBRST
(Note 5)
PBRST
Delay
Reset Active Time
ST
Pulse Width
ST
Timeout Period
V
CC
Fall Time (Note 4)
V
CC
Rise Time (Note 4)
V
CC
Detect to RST High and
RST
Low
V
CC
Detect to RST Low and
RST
Open (Note 6)
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
SYMBOL
t
PB
t
PBD
t
RST
t
ST
t
TD
t
F
t
B
t
BPD
t
BPU
Figure 4
Figure 4, TD pin = 0V
TD pin = open
TD pin = V
CC
Figure 5
Figure 6
Figure 7, V
CC
falling
Figure 8, V
CC
rising
250
610
Figure 3
Figure 3
CONDITIONS
MIN
20
1
250
75
62.5
250
500
10
0
100
1000
150
600
1200
250
1000
2000
µs
µs
ns
ms
ms
4
610
20
1000
TYP
MAX
UNITS
ms
ms
ms
ns
PBRST
is internally pulled up to V
CC
with an internal impedance of typically 40kΩ.
Measured with outputs open.
All voltages referenced to GND.
Guaranteed by design.
PBRST
must be held low for a minimum of 20ms to guarantee a reset.
t
R
= 5μs.
Pin Description
PIN
WIDE SO
1, 3, 5, 7, 10,
12, 14, 16
2
4
6
8
DIP/SO
—
1
2
3
4
NAME
N.C.
PBRST
TD
TOL
GND
No Connection
Pushbutton Reset Input. A debounced active-low input that ignores pulses less than 1ms
in duration and is guaranteed to recognize inputs of 20ms or greater.
Time Delay Set. The watchdog timebase select input (t
TD
= 150ms for TD = 0V,
t
TD
= 600ms for TD = open, t
TD
= 1.2s for TD = V
CC
).
Tolerance Input. Connect to GND for 5% tolerance or to V
CC
for 10% tolerance.
Ground
Reset Output (Active High). Goes active:
(1) If V
CC
falls below the selected reset voltage threshold.
(2) If
PBRST
is forced low.
(3) If
ST
is not strobed within the minimum timeout period.
(4) During power-up.
Reset Output (Active Low, Open Drain). See RST.
Strobe Input. Input for watchdog timer.
+5V Power-Supply Input
FUNCTION
9
5
RST
11
13
15
6
7
8
RST
ST
V
CC
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