MAX1232
Microprocessor Monitor
Detailed Description
Power Monitor
A voltage detector monitors V
CC
and holds the reset
outputs (RST and
RST)
in their active states whenever
V
CC
is below the selected 5% or 10% tolerance (4.62V
or 4.37V, typically). To select the 5% level, connect TOL
to ground. To select the 10% level, connect TOL to V
CC
.
The reset outputs will remain in their active states until
V
CC
has been continuously in-tolerance for a minimum of
250ms (the reset active time) to allow the power supply
and μP to stabilize.
The RST output both sinks and sources current, while the
RST
output, an open-drain MOSFET, sinks current only
and must be pulled high.
Watchdog Timer
The microprocessor drives the
ST
input with an input/
output (I/O) line. The microprocessor must toggle the
ST
input within a set period (as determined by TD) to verify
proper software execution. If a hardware or software fail-
ure keeps
ST
from toggling within the minimum timeout
period—ST is activated only by falling edges (a high-to-
low transition)—the MAX1232 reset outputs are forced to
their active states for 250ms (Figure 2). This typically initi-
ates the microprocessor’s power-up routine. If the inter-
ruption continues, new reset pulses are generated each
timeout period until
ST
is strobed. The timeout period is
determined by the TD input connection. This timeout peri-
od is typically 150ms with TD connected to GND, 600ms
with TD floating, or 1200ms with TD connected to V
CC
.
The software routine that strobes
ST
is critical. The code
must be in a section of software that executes frequently
enough so the time between toggles is less than the
watchdog timeout period. One common technique con-
trols the microprocessor I/O line from two sections of the
program. The software might set the I/O line high while
operating in the foreground mode, and set it low while in
the background or interrupt mode. If both modes do not
execute correctly, the watchdog timer issues reset pulses.
Pushbutton Reset Input
The MAX1232’s debounced manual reset input (PBRST)
manually forces the reset outputs into their active states.
The reset outputs go active after
PBRST
has been held
low for a time t
PBD
, the pushbutton reset delay time. The
reset outputs remain in their active states for a minimum
of 250ms after
PBRST
rises above V
IH
(Figure 3).
A mechanical pushbutton or an active logic signal can
drive the
PBRST
input. The debounced input ignores
input pulses less than 1ms and is guaranteed to recog-
nize pulses of 20ms or greater. The
PBRST
input has
an internal pullup to V
CC
of about 100μA; therefore, an
external pullup resistor is not necessary.
+5V
+5V
10kΩ
V
CC
PB RST
TD
ST
RST
I/O
MICROPROCESSOR
RESET
+8V
7805
+5V
3-TERMINAL
REGULATOR
V
CC
0.10µF
RST
RESET
MICROPROCESSOR
ST
TD
TOL
GND
I/O
MAX1232
MAX1232
GND
TOL
Figure 1. Pushbutton Reset
Figure 2. Watchdog Timer
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