S w it c h e d -Ca p a c it o r Vo lt a g e Co n ve rt e rs
MAX14/ICL760
P a ra lle lin g De vic e s
Paralleling multiple MAX1044/ICL7660s reduces output
resistance and increases current capability. As illus-
trated in Figure 13, each device requires its own pump
capacitor C1, but the reservoir capacitor C2 serves all
devices. The equation for calculating output resistance is:
1
2
3
4
8
7
6
5
V+
MAX1044
ICL7660
C1
R
(of MAX1044 or ICL7660)
OUT
n (number of devices)
R
=
OUT
1
S h u t d o w n S c h e m e s
Figures 14a–14c illustrate three ways of adding shut-
down capability to the MAX1044/ICL7660. When using
these circuits, be aware that the additional capacitive
loading on the OSC pin will reduce the oscillator fre-
quency. The first circuit has the least loading on the
OSC pin and has the added advantage of controlling
shutdown with a high or low logic level, depending on
the orientation of the switching diode.
1
2
3
4
8
7
6
5
MAX1044
ICL7660
V
= -(V+)
OUT
C1
C2
n
Figure 13. Paralleling MAX1044/ICL7660 to Reduce Output
Resistance
_Ord e rin g In fo rm a t io n (c o n t in u e d )
V+
10kΩ REQUIRED FOR TTL
PART
TEMP. RANGE
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
PIN-PACKAGE
8 SO
V+
CMOS or
TTL GATE
1
2
3
4
8
7
6
5
MAX1044ESA
MAX1044MJA
ICL7660CPA
ICL7660CSA
ICL7660CUA
ICL7660C/D
ICL7660EPA
ICL7660ESA
1N4148
8 CERDIP**
8 Plastic DIP
8 SO
MAX1044
ICL7660
10µF
0°C to +70°C
0°C to +70°C
8 µMAX
0°C to +70°C
Dice*
V
OUT
= -(V+)
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
8 Plastic DIP
8 SO
10µF
†
a)
ICL7660AMJA
8 CERDIP**
8 TO-99**
†
V+
ICL7660AMTV
74HC03
OPEN-DRAIN OR
74LS03
OPEN-COLLECTOR
NAND GATES
* Contact factory for dice specifications.
MAX1044
ICL7660
7
** Contact factory for availability.
†
The Maxim ICL7660 meets or exceeds all “A” and “S”
specifications.
b)
c)
V+
OUTPUT
ENABLE
74HC126 OR
74LS126
TRI-STATE BUFFER
MAX1044
ICL7660
7
Figure 14a-14c. Shutdown Schemes for MAX1044/ICL7660
______________________________________________________________________________________ 11