DS2781
1-Wire SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2781
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data.
All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2781 is shown in Figure 26. A
presence pulse following a reset pulse indicates that the DS2781 is ready to accept a net address command. The
bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and goes into receive mode
(Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin,
the DS2781 waits for tPDH and then transmits the presence pulse for tPDL
.
Figure 26. 1-Wire Initialization Sequence
tRSTL
tRSTH
tPDH
tPDL
PACK+
PACK-
DQ
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
DS2781 ACTIVE LOW
RESISTOR PULLUP
BOTH BUS MASTER AND
DS2781 ACTIVE LOW
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be tSLOT in duration with a
1μs minimum recovery time, tREC, between cycles. The DS2781 samples the 1-Wire bus line between 15μs and
60μs (between 2μs and 6μs for overdrive speed) after the line falls. If the line is high when sampled, a write 1
occurs. If the line is low when sampled, a write 0 occurs (see Figure 27). For the bus master to generate a write 1
time slot, the bus line must be pulled low and then released, allowing the line to be pulled high within 15μs (2μs for
overdrive speed) after the start of the write-time slot. For the host to generate a write 0 time slot, the bus line must
be pulled low and held low for the duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1μs and then release it to allow the DS2781 to present valid
data. The bus master can then sample the data tRDV from the start of the read-time slot. By the end of the read-time
slot, the DS2781 releases the bus line and allows it to be pulled high by the external pullup resistor. All read-time
slots must be tSLOT in duration with a 1μs minimum recovery time, tREC, between cycles. See Figure 27 for more
information.
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
