DS2154
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex)
(MSB)
(LSB)
TIDR0
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR.7
TIDR.0
MSB of the Idle Code (this bit is transmitted first).
LSB of the Idle Code (this bit is transmitted last).
TIDR0
9.1.2 Per-Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code
to be placed into each of the 32 E1 channels.
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address = 60 to 7F Hex)
(For brevity, only channel 1 is shown; see Table 2-1 for other register address.)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
TC1 (60)
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
TC1.7
MSB of the Code (this bit is transmitted first).
LSB of the Code (this bit is transmitted last).
C0
TC1.0
TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address = A0 to A3 Hex)
(MSB)
CH8
CH16
CH24
CH32
(LSB)
CH1
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
TCC1 (A0)
TCC2 (A1)
TCC3 (A2)
TCC4 (A3)
CH9
CH17
CH25
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1
TCC1.0
Transmit Channel 1 Code Insertion Control Bit
0 = do not insert data from the TC1 register into the transmit data
stream
1 = insert data from the TC1 register into the transmit data stream
CH32
TCC4.7
Transmit Channel 32 Code Insertion Control Bit
0 = do not insert data from the TC32 register into the transmit data
stream
1 = insert data from the TC32 register into the transmit data stream
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
