Real-Time Clocks
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. INPUT VOLTAGE
DS17285/87 toc01
SUPPLY CURRENT
vs. TEMPERATURE
V
BAT
= 3.0V
SUPPLY CURRENT (nA)
DS17285/87 toc02
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
DS17285/87 toc03
400
V
CC
= 0V
350
400
32768.7
32768.6
OSCILLATOR FREQUENCY (Hz)
32768.5
32768.4
32768.3
32768.2
32768.1
SUPPLY CURRENT (nA)
350
300
300
250
200
2.5
2.8
3.0
3.3
3.5
3.8
V
BAT
(V)
250
-40
-25 -10
5
20
35
50
65
80
TEMPERATURE (°C)
32768.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
Pin Description
PIN
24
28
NAME
FUNCTION
Active-Low Power-On Reset. This open-drain output pin is intended for use as an on/off control
for the system power. With V
CC
voltage removed from the device,
PWR
can be automatically
activated from a kickstart input by the
KS
pin or from a wake-up interrupt. Once the system is
powered on, the state of
PWR
can be controlled by bits in the control registers. The
PWR
pin
can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage
of the pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the
pullup supply should be no greater than 3.9V.
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (C
L
) of 6pF or
12.5pF. Pin X1 is the input to the oscillator and can optionally be connected to an external
32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external
oscillator is connected to pin X1. These pins are missing (N.C.) on the EDIP package.
1
8
PWR
2, 3
9, 10
X1, X2
4–11
12–17,
19, 20
Multiplexed Bidirectional Address/Data Bus. The addresses are presented during the first
portion of the bus cycle and latched into the device by the falling edge of ALE. Write data is
AD0–AD7 latched by the rising edge of
WR.
In a read cycle, the device outputs data during the latter
portion of the
RD
low. The read cycle is terminated and the bus returns to a high-impedance
state as
RD
transitions high.
GND
Ground
12, 16
21, 22, 26
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7
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