DS1337 I
2
C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 1.8V to 5.5V, T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
SCL Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition (Note 10)
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
(Notes 11, 12)
Data Setup Time (Note 13)
Rise Time of Both SDA and
SCL Signals (Note 14)
Fall Time of Both SDA and
SCL Signals (Note 14)
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
I/O Capacitance (SDA, SCL)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
C
B
C
I/O
CONDITIONS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 14)
(Note 15)
MIN
100
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.6
4.0
TYP
MAX
400
100
UNITS
kHz
µs
µs
µs
µs
µs
0.9
µs
ns
300
1000
300
300
ns
ns
µs
400
10
pF
pF
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA,
INTA,
and SQW/INTB.
I
CCA
—SCL clocking at max frequency = 400kHz, V
IL
= 0.0V, V
IH
= V
CC.
Specified with the I C bus inactive, V
IL
= 0.0V, V
IH
= V
CC.
SQW enabled.
Specified with the SQW function disabled by setting INTCN = 1.
Using recommended crystal on X1 and X2.
The device is fully accessible when 1.8
≤
V
CC
≤
5.5V. Time and date are maintained when 1.3V
≤
V
CC
≤
1.8V.
After this period, the first clock pulse is generated
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
≥
to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R max
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL
line is released.
C
B
—total capacitance of one bus line in pF.
Guaranteed by design. Not production tested.
2
Note 14:
Note 15:
3 of 15
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
