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DS1305E/T&R 参数 Datasheet PDF下载

DS1305E/T&R图片预览
型号: DS1305E/T&R
PDF下载: 下载PDF文件 查看货源
内容描述: [Real Time Clock, Volatile, 0 Timer(s), CMOS, PDSO20, 0.173 INCH, TSSOP-20]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管闹钟
文件页数/大小: 22 页 / 307 K
品牌: MAXIM [ MAXIM INTEGRATED PRODUCTS ]
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DS1305  
ADDRESS AND DATA BYTES  
Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data  
output (SDO). Any transfer requires the address of the byte to specify a write or read to either a RTC or  
RAM location, followed by one or more bytes of data. Data is transferred out of the SDO for a read  
operation and into the SDI for a write operation (Figures 6 and 7).  
Figure 6. SPI SINGLE-BYTE WRITE  
* SCLK CAN BE EITHER POLARITY.  
SERMODE = VCC  
Figure 7. SPI SINGLE-BYTE READ  
* SCLK CAN BE EITHER POLARITY.  
SERMODE = VCC  
The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of  
this byte determines if a read or write takes place. If A7 is 0, one or more read cycles occur. If A7 is 1,  
one or more write cycles occur.  
Data transfers can occur one byte at a time or in multiple-byte burst mode. After CE is driven high an  
address is written to the DS1305. After the address, one or more data bytes can be written or read. For a  
single-byte transfer, one byte is read or written and then CE is driven low. For a multiple-byte transfer,  
however, multiple bytes can be read or written to the DS1305 after the address has been written. Each  
read or write cycle causes the RTC register or RAM address to automatically increment. Incrementing  
continues until the device is disabled. When the RTC is selected, the address wraps to 00h after  
incrementing to 1Fh (during a read) and wraps to 80h after incrementing to 9Fh (during a write). When  
the RAM is selected, the address wraps to 20h after incrementing to 7Fh (during a read) and wraps to  
A0h after incrementing to FFh (during a write).  
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