DS1307 64 x 8, Serial, I
2
C Real-Time Clock
Figure 6. Data Read (Write Pointer, Then Read)—Slave Receive and Transmit
<RW>
<Slave Address>
<Word Address (n)>
<Slave Address>
<RW>
S
1101000
0
A XXXXXXXX
<Data(n+1)>
A Sr
1101000
1
A
<Data(n+X)>
<Data(n)>
<Data(n+2)>
XXXXXXXX
A XXXXXXXX
A XXXXXXXX
Master to slave
Slave to master
A ... XXXXXXXX
A P
S - Start
Sr - Repeated Start
A - Acknowledge (ACK)
P - Stop
A
- Not Acknowledge (NACK)
DATA TRANSFERRED
(X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS
FOLLOWED BY A NOT ACKNOWLEDGE (A) SIGNAL)
TYPICAL OPERATING CIRCUIT
V
CC
CRYSTAL
V
CC
R
PU
R
PU
V
CC
X1
SCL
CPU
X2
V
CC
SQW/OUT
DS1307
SDA
GND
R
PU
= t
r
/C
b
V
BAT
PIN CONFIGURATIONS
TOP VIEW
X1
X2
V
BAT
GND
1
DS1307
2
3
4
8
7
6
5
V
CC
SQW/OUT
SCL
SDA
X1
X2
V
BAT
GND
1
DS1307
2
3
4
8
7
6
5
V
CC
SQW/OUT
SCL
SDA
PDIP (300 mils)
SO (150 mils)
13 of 15
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
