DS1216D 参数 Datasheet PDF下载

DS1216 SmartWatch RAM/SmartWatch ROM

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues

for 64 write cycles as described above until all the bits in the comparison register have been matched (this

bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data

transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch

to either receive or transmit data on DQ0, depending on the level of the

OE

pin or the

WE

pin. Cycles to

other locations outside the memory block can be interleaved with

CE

cycles without interrupting the

pattern recognition sequence or data transfer sequence to the SmartWatch.

PATTERN MATCH—ROM

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits

that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the

proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior

to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read

cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition

starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of

the 64-bit comparison register. If a match is found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues

for a total of 64 write cycles as described above, until all the bits in the comparison register have been

matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is

enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause

the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on

the level of /WRITE READ (A2).

After power-up, the controller could be in the 64-bit clock register read/write sequence (from an

incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed

upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to

the RAM would otherwise be expected.

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