Improved, Quad, SPST Analog Switches
DG441/DG442
Pin Description
PIN
DIP/SO
1, 16, 9,
8
2, 15,
10, 7
3, 14,
11, 6
4
5
12
13
THIN
QFN-EP
15, 14,
7, 6
16, 13,
8, 5
1, 12, 9,
4
2
3
10
11
NAME
FUNCTION
plies. (Switching times increase by a factor of two or
more for operation at ±5V.)
Overvoltage Protection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
Always sequence V+ on first, followed by V- and logic
inputs. If power-supply sequencing is not possible, add
two small, external signal diodes in series with supply
pins for overvoltage protection (Figure 1). Adding exter-
nal diodes reduces the analog-signal range to 1V
below V+ and 1V above V-, but low switch resistance
and low leakage characteristics are unaffected. Device
operation is unchanged, and the difference between
V+ and V- should not exceed +44V.
IN1–IN4 Input
D1–D4
S1–S4
V-
GND
N.C.
V+
Analog Switch Drain Terminal
Analog Switch Source
Terminal
Negative-Supply Voltage Input
Ground
Not Internally Connected
Positive-Supply Voltage
Input—Connected to Substrate
Exposed Pad. Connect EP to
V+. Do not use EP as a sole
V+ connection. (Thin QFN
package only.)
V+
—
—
EP
Applications Information
Operation with Supply Voltages
Other Than ±15V
Using supply voltages other than ±15V reduces the
analog signal range. The DG441/DG442 switches oper-
ate with ±4.5V to ±20V bipolar supplies or with a +10V
to +30V single supply; connect V- to 0V when operating
with a single supply. Also, all device types can operate
with unbalanced supplies such as +24V and -5V. The
Typical Operating Characteristics
graphs show typical
on-resistance with ±20V, ±15V, ±10V, and ±5V sup-
Vg
D
S
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
6
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