Improved, Quad, SPST Analog Switches
______________________________________________Timing Diagrams/Test Circuits
+15V
LOGIC
INPUT
+3V
50%
0V
tOFF
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
+3V
GND
V-
t
f
< 20ns
t
r
< 20ns
SWITCH
INPUT
V+
V
D
D
IN
S
DG441/DG442
DG441
DG442
VOUT
RL
35pF
0.8 x VOUT
0.8 x VOUT
-15V
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
CL (INCLUDES FIXTURE AND STRAY CAPACITANCE)
R
L
VOUT = VD
R
L
+ rDS(ON)
0V
tON
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
(
)
Figure 2. Switching Time
∆V
OUT
VOUT
IN
DG441
RGEN
+15V
V+
S
D
DG441
DG442
VOUT
CL
1nF
OFF
ON
OFF
VGEN
GND
IN
V-
-15V
VIN = +3V
OFF
IN
DG442
ON
Q =
∆V
OUT
×
CL
OFF
Figure 3. Charge Injection
10nF
+15V
10nF
+15V
DG441
DG442
SIGNAL
GENERATOR
10dBm
D
V+
SIGNAL
GENERATOR
10dBm
V+
D
S
DG441
DG442
50Ω
RGEN = 50Ω
IN
0.8V or 2.4V
NETWORK
ANALYZER
RL
-15V
S
GND
V-
10nF
RGEN = 50Ω
0.8V or 2.4V
IN1
S
GND
RL
-15V
V-
IN2
0.8V or 2.4V
NETWORK
ANALYZER
D
10nF
Figure 4. Off-Isolation Rejection Ratio
Figure 5. Crosstalk (repeat for channels 3 and 4)
7
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
