Improved, Quad,
SPST Analog Switches
Pin Description
PIN
NAME
FUNCTION
DIP/SO/TSSOP
QFN
1, 16, 9, 8
15, 14, 7, 6
IN1–IN4 Input
2, 15, 10, 7
16, 13, 8, 5
D1–D4 Analog Switch Drain Terminal
S1–S4 Analog Switch Source Terminal
3, 14, 11, 6
1, 12, 9, 4
4
2
V-
Negative-Supply Voltage Input
Ground
5
3
GND
12
13
—
10
11
—
V
Logic Supply Voltage
L
V+
EP
Positive-Supply Voltage Input—Connected to Substrate
Exposed Paddle (QFN Only). Connect EP to V+.
Adding diodes reduces the analog signal range to 1V
below V+ and 1V below V-, without affecting low switch
resistance and low leakage characteristics. Device
operation is unchanged, and the difference between
V+ and V- should not exceed +44V.
__________Applications Information
2/DG413
Operation with Supply Voltages
Other Than 15V
Using supply voltages other than 15V will reduce the
analog signal range. The DG411/DG412/DG413 switch-
es operate with 4.5V to 20V bipolar supplies or with
a +10V to +30V single supply; connect V- to 0V when
operating with a single supply. Also, all device types
can operate with unbalanced supplies such as +24V
V+
and -5V. V must be connected to +5V to be TTL com-
L
patible, or to V+ for CMOS-logic level inputs. The
Typical Operating Characteristics graphs show typical
on-resistance with 15V, 10V, and 5V supplies.
(Switching times increase by a factor of two or more for
operation at 5V.)
V+
D
S
Overvoltage Protection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings because stresses beyond the listed rat-
ings may cause permanent damage to the devices.
V
g
V-
Always sequence V+ on first, followed by V , V-, and
L
V-
logic inputs. If power-supply sequencing is not possi-
ble, add two small, external signal diodes in series with
supply pins for overvoltage protection (Figure 1).
Figure 1. Overvoltage Protection Using External Blocking Diodes
6
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