Improved, Quad,
SPST Analog Switches
______________________________________________Timing Diagrams/Test Circuits
+5V
LOGIC
INPUT
+3V
50%
0V
t r < 20ns
t f < 20ns
SWITCH
INPUT
t
OFF
IN1
V
OUT
SWITCH
OUTPUT
0V
t
ON
0.9 x V
OUT
0.9 x V
OUT
LOGIC
INPUT
GND
0V
V-
-15V
S1
V
L
+15V
V+
D1
R
L
300Ω
DG411/DG412/DG413
DG411
DG412
DG413
SWITCH OUTPUT
V
OUT
C
L
35pF
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
REPEAT TEST FOR IN AND S, FOR LOAD
CONDITIONS, SEE
Electrical Characteristics.
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
R
L
V
OUT
= V
S
R
L
+ r
DS(ON)
(
)
Figure 2. Switching-Time
LOGIC
INPUT
+3V
50%
0V
S1
V
S1
= +10V
V
S2
= +10V
S2
IN
0.9 x VOUT2
0V
tD
tD
LOGIC
INPUT
+5V
V
L
+15V
V+
DG413
D1
D2
R
L2
V
OUT2
C
L2
R
L1
V
OUT1
C
L1
SWITCH
OUTPUT 1
(VO1)
SWITCH
OUTPUT 2
(VO2)
0.9 x VOUT1
0V
GND
V-
-15V
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
R
L
= 300Ω
C
L
= 35pF
Figure 3. DG413 Break-Before-Make
∆V
OUT
VOUT
IN
OFF
ON
OFF
V GEN
R
GEN
+5V
V
L
S
+15V
V+
D
CL
DG411
DG412
DG413
VOUT
GND
IN
V-
IN
OFF
ON
Q = (∆V OUT )(C L )
OFF
-15V
V
IN
= +3V
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge-Injection
_______________________________________________________________________________________
7
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
