Quad SPST CMOS Analog Switches
DG201A/DG211
LOGIC
INPUT
t
f
< 20ns
t
r
< 20ns
3V
50%
0
SWITCH
INPUT
V
S
= +2V
SWITCH
INPUT
V
S
V
0
0
t
ON
0.9
V
0
V
0
t
off1
t
off2
0
0.9
0.1
LOGIC IN
1
INPUT
Ω
GND
V-
-15V
S
1
LOGIC "0" - SW ON
+15V
V+
D
1
R
L
1kΩ
R
L
V
0
= V
S
R + R
L
DS(ON)
SWITCH
OUTPUT
V
0
C
L
35pF
SWITCH
OUTPUT
(REPEAT TEST FOR IN
2
, IN
3
, AND IN
4
)
Figure 1. Switching Time
Typical R
DS(ON)
vs. Power Supplies for Maxim’s DG201A, and DG211
POWER SUPPLIES
±5V
±10V
±15V
R
DS(ON)
AT ANALOG SIGNAL LEVEL
-5V
350Ω
—
—
+5V
380Ω
—
—
-10V
—
165Ω
125Ω
+10V
—
250Ω
160Ω
-15V
—
—
135Ω
+15V
—
—
155Ω
Protecting Against Fault
Conditions
Fault conditions occur when power supplies are turned
off when input signals are still present, or when over-
voltages occur at the inputs during normal operation. In
either case, source-to-body diodes can be forward
biased and conduct current from the signal source. If
this current is required to be kept to low (µA) levels
then the addition of external protection diodes is rec-
ommended.
To provide protection for overvoltages up to 20V above
the supplies, a 1N4001 or 1N914 type diode should be
placed in series with the positive and negative supplies
as shown in Figure 2. The addition of these diodes will
reduce the analog signal range to 1V below the posi-
tive supply and 1V above the negative supply.
1
2
IN4001
-15V
3
4
5
16
15
14
IN4001
+15V
Pin Configurations (continued)
TOP VIEW
D1
16
IN1
15
IN2
14
D2
13
DG201A
DG211
13
12
11
10
9
6
7
8
S1
V-
GND
S4
1
2
12
11
S2
V+
N.C.
S3
Figure 2. Protection against Fault Conditions
DG201A
DG211
3
4
5
D4
6
IN4
7
IN3
8
D3
10
9
QFN*
6
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
