78M6610+LMU Data Sheet
Power-On and Reset Circuitry
An on-chip power-on reset (POR) block monitors the supply voltage (V3P3D) and initializes the internal
digital circuitry at power-on. Once V3P3D is above the minimum operating threshold, the POR circuit
triggers and initiates a reset sequence. It will also issue a reset to the digital circuitry if the supply voltage
falls below the minimum operating level.
In addition to the internal sources, a reset can be forced by applying a low level to the RESET pin. If the
RESET pin is pulled low, all digital activities in the device stop, except the clock management circuitry
and oscillators, which continue to run. The external reset input is filtered to prevent spurious reset events
in noisy environments. The reset does not occur until RESET has been held low for at least 1µs.
Once initiated, the reset mode persists until the RESET is set high and the reset timer times out (4096
clock cycles). At the completion of the reset sequence, the internal reset is released and the processor
(EMP) begins executing from address 0.
If not used, the RESET pin can be connected either directly or through a pullup resistor to V3P3D supply. A
simple connection diagram is shown below.
V3P3
V3P3
V
V
3P3D
3P3D
10KΩ
RESET
RESET
Manual
Reset Switch
1nF
GNDD
GNDD
78M6610+LMU
78M6610+LMU
GND
GND
b) Unused R
ESET
Connection Example
a) External R
ESET
Connection Example
Figure 7. Reset Connections
Watchdog Timer
A Watchdog Timer (WDT) block detects any software processing errors. The software periodically
refreshes the free-running watchdog timer to prevent it from timing out. If the WDT times out, it is an
indication that software is no longer being executed in the intended sequence; thus, a system reset is
initiated.
14
Rev 0
MAXIM [ MAXIM INTEGRATED PRODUCTS ]
