MCP795WXX/MCP795BXX
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
9.1.10
DATA PROTECTION
The following protection has been implemented to pre-
vent inadvertent writes to the array:
• Access to the array during an internal EEPROM
write cycle is ignored and programming is contin-
ued
• The write enable latch is reset on power-up
• A Write Enable instruction must be issued to set
the write enable latch
• Block protect bits are ignored for UID writes
• After a byte write, page write, unique ID write, or
STATUS register write, the write enable latch is
reset
9.1.11
CLEAR WATCHDOG INSTRUCTION
The Clear Watchdog command resets the internal
Watchdog Timer.
FIGURE 9-7:
CLRWDT
CS
0
1
2
3
4
5
6
7
SCK
SI
0
1
0
0
0
1
0
0
High-Impedance
SO
9.1.12
CLEAR RAM INSTRUCTION
The Clear Ram instruction is a 2-byte command that
will reset the internal SRAM to the known value. Using
this command, all locations in the SRAM are set to 00h
and the data value contained in the second byte of the
command is ignored.
FIGURE 9-8:
CLRRAM
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
Data
0
1
0
1
0
1
0
0
A7
6
5
4
3
2
1
A0
High-Impedance
SO
DS22280A-page 36
Preliminary
2011 Microchip Technology Inc.
MAS [ MICRO ANALOG SYSTEMS ]
