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MCP795B20 参数 Datasheet PDF下载

MCP795B20图片预览
型号: MCP795B20
PDF下载: 下载PDF文件 查看货源
内容描述: SPI实时时钟日历 [SPI Real-Time Clock Calendar]
分类和应用: 时钟
文件页数/大小: 54 页 / 969 K
品牌: MAS [ MICRO ANALOG SYSTEMS ]
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MCP795WXX/MCP795BXX  
The debounce will only operate if the clock is running  
and these timings are based on the uncalibrated  
32.768 kHz clock.  
TABLE 9-1:  
VBAT CHANGOVER  
CONDITIONS  
Supply  
Condition  
Read/Write Powered  
Access  
• EVHS<1:0> – These bits determine how many  
high-speed events must occur before the EVHIF  
bit is set. All of these events must occur within  
250 ms.  
By  
VCC < VTRIP, VCC < VBAT  
VCC > VTRIP, VCC < VBAT  
VCC > VTRIP, VCC > VBAT  
No  
Yes  
Yes  
VBAT  
VCC  
VCC  
- 00– 1st Event  
- 01– 4th Event  
- 10– 16th Event  
- 11– 32nd Event  
For more information on VBAT conditions see the RTCC  
Best Practices Application Note, AN1365 (DS01365).  
9.1.6  
UNIQUE ID LOCATIONS  
9.1.5  
VBAT SWITCHOVER  
When the unique ID locations are preprogrammed from  
the factory with either an EUI-48 or EUI-64, the EUI  
code is programmed into location 0x00-0x07. Loca-  
tions 0x08-0x0F are blank (0x0F).  
If the VBAT feature is not used, the VBAT pin should be  
connected to GND. A low value series resistor and  
Schottky diode are recommended between the  
external battery and the VBAT pin to reduce inrush  
current and also to prevent any leakage current  
reaching the external VBAT source.  
Note:  
For EUI-64, the data is located in address  
0x00-0x07. For EUI-48 locations, 0x02-  
0x07 contain the data. 0x00/01 contain  
0xFF.  
The VTRIP point is defined as 1.5V typical. When VDD  
falls below 1.5V the system will continue to operate  
the RTCC and SRAM using the VBAT supply. There is  
~50mV hyst in the trip point changeover. The following  
conditions apply:  
To read the unique ID location the IDREAD command  
is given with the starting address. Valid addresses are  
0x00 through 0x0F. All 16 bytes can be read out in a  
single command by clocking the device. Trying to  
access locations past 0x0F will result in the address  
wrapping within these 16 bytes.  
FIGURE 9-2:  
IDREAD COMMAND SEQUENCE  
CS  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23  
SCK  
SI  
Instruction  
Address Byte  
0
0
1
1
0
0
1
1
0
0
0
0
3
2
1
0
Don’t Care  
Data Out  
High-Impedance  
7
6
5
4
3
2
1
0
SO  
Address range is 0x00-0x0F, address counter will wrap within this range.  
To write to the unique ID locations, the IDWRITE com-  
mand is used. The device must be write enabled and  
the correct unlock sequence must have been per-  
formed. See Section 10.1.4, Write to the Unlock  
Register for more details.  
The ID locations can be written to using the IDWRITE  
command. The valid address is between 0x00 and  
0x0F. The entire 16 bytes must be written in two  
groups of 8 bytes. A maximum of 8 bytes can be  
written at once.  
2011 Microchip Technology Inc.  
Preliminary  
DS22280A-page 31  
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