MCP795WXX/MCP795BXX
The following is a list of conditions under which the
write enable latch will be reset:
3.3
Write Enable (EEWREN) and Write
Disable (EEWRDI)
• Power-up
The MCP795XXX contains a write enable latch.
• EEWRDIinstruction successfully executed
• SRWRITEinstruction successfully executed
• EEWRITEinstruction successfully executed
• IDWRITEinstruction successfully executed
This latch must be set before any EEWRITE,
SRWRITE and IDWRITE operation will be completed
internally. The EEWRENinstruction will set the latch, and
the EEWRDIwill reset the latch.
FIGURE 3-4:
WRITE ENABLE SEQUENCE (EEWREN)
CS
SCK
SI
0
1
2
3
4
5
6
7
0
0
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5:
WRITE DISABLE SEQUENCE (EEWRDI)
CS
0
1
2
3
4
5
6
7
SCK
0
0
0
0
0
0
1
0
SI
High-Impedance
SO
DS22280A-page 10
Preliminary
2011 Microchip Technology Inc.
MAS [ MICRO ANALOG SYSTEMS ]
