MCP7952X/MCP7951X
The frequencies listed in the table presume an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
9.1
Features
9.1.1
CALIBRATION
The Calibration register (0x09h) allows a number of
RTCC counts to be added or subtracted (CALSGN bit
located at 0x03:7) each minute. This allows for
calibration to reduce the PPM error due to oscillator
shift. This register is volatile.
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
32768
8
4
1
The CALSGN bit determines if calibration is positive or
negative.
A value of 0x00 in the Calibration register will result in
no calibration.
With regards to the calibration function, the Calibration
register setting has no impact upon the MFP output
clock signal when bits RS1 and RS0 are set to ‘11’.
The setting of the Calibration register to a non-zero
value enables the calibration function which can be
observed on the MFP output pin. The calibration
function can be expressed in terms of the number of
input clock cycles added/subtracted from the internal
timing function.
The calibration is linear, with one bit representing two
RTC clocks.
The MCP795XX utilizes digital calibration to correct for
the inaccuracies of the input clock source (either
external or crystal). Calibration is enabled by setting
the value of the Calibration register at address 08H.
Calibration is achieved by adding or subtracting a
number of input clock cycles per minute in order to
achieve ppm level adjustments in the internal timing
function of the MCP795XX.
With bits RS1 and RS0 set to ‘00’, the calibration
function can be expressed as:
Toutput
where:
Toutput
Tinput
=
(32768 +/- (2 * CALREG)) Tinput
The CALSGN bit is the calibration sign bit, with a ‘1’
indicating subtraction and a ‘0’ indicating addition. The
eight bits in the Calibration register indicate the
number of input clock cycles (multiplied by two) that
are subtracted or added per minute to the internal
timing function.
=
=
=
clock period of MFP output signal
clock period of input signal
CALREG
decimal value of Calibration
register setting and the sign is
determined by the CALSGN bit.
The internal timing function can be monitored using
the MFP output pin by setting bit 6 (SQWE) and bits
<2:0> (RS2, RS1, RS0) of the Control register at
address 07H. Note that the MFP output waveform is
disabled when the MCP795XX is running in VBAT
mode. With the SQWE bit set to ‘1’, there are two
methods that can be used to observe the internal
timing function of the MCP795XX:
Since the calibration is done once per minute (i.e.,
when the internal minute counter is incremented), only
one cycle in sixty of the MFP output waveform is
affected by the calibration setting. Also note that the
duty cycle of the MFP output waveform will not
necessarily be at 50% when the calibration setting is
applied.
Method 1. RS2 bit set to ‘0’
With bits RS1 and RS0 set to ‘01’ or ‘10’, the
calibration function can not be expressed in terms of
the input clock period. In the case where the MSB of
the Calibration register is set to ‘0’, the waveform
appearing at the MFP output pin will be “delayed”, once
per minute, by twice the number of input clock cycles
defined in the Calibration register. The MFP waveform
will appear as shown in Figure 9-1.
With the RS2 bit set to ‘0’, the RS1 and RS0 bits
enable the following internal timing signals to be
output on the MFP pin:
RS2
RS1
RS0
Output Signal
1 Hz
0
0
0
0
0
0
1
1
0
1
0
1
4.096 kHz
8.192 kHz
32.768 kHz
DS22300A-page 26
Preliminary
2012 Microchip Technology Inc.
MAS [ MICRO ANALOG SYSTEMS ]
