DA9191A.000
July 31, 1997
FUNCTIONS
◆ Data Reception
The data reception block is in the power down state
after a reset. The power down mode of the block is
controlled by the RXSIP bit in register 07HEX. The
Manchester encoded data is received through the RX
pin. The data is amplified with GC1 and filtered with
filter F1. The comparator C1 is used to convert data to
a digital signal. The digital PLL circuit recovers the bit
clock from the Manchester encoded data. The bit
clock is 8kHz in the ETACS mode and 10kHz in the
AMPS mode. The mode is set with the SYS0 bit of
register 12HEX. The recovered bit clock is used in the
Manchester decoder and the data is then transmitted
to the frame decoding block. The frame decoding
block finds dotting sequences, busy/idle bits and word
syncs from the data. To avoid data being generated
by random noise, the frame decoding block enters the
data reception mode only after it has received two
consecutive word syncs (11100010010) separated by
463 bits in the forward control channel and 77 bits in
the forward voice channel. In this case the voting and
BCH block are activated. When the frame decoding
block loses five consecutive synchronization patterns
it rejects the data reception mode and sets the voting
and BCH blocks in power down state. The voice and
control channel modes are selected with the CTCV bit
of register 12HEX
.
Forward control channel data format. The numbers under the frames show the number of bits in each section.
Busy/
Idle
1
Bit
Sync
10
Busy/
Idle
1
Word
Sync
11
Busy/
Idle
1
Data
Busy/
Idle
1
Data
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
10
10
1. Repeat of word A
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
1. Repeat of word B
2. Repeat of word A
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Idle
1
Data
10
Busy/
Bit
Sync
10
Busy/
Idle
1
Idle
1
5. Repeat of word B
bit sync = 1010101010
word sync = 11100010010
The busy/idle bits are extracted from the data.
Busy/idle bits are used to indicate the current status
of the reverse control channel (RECC). The RECC is
busy if the busy/idle bit is low and idle if the busy/idle
bit is high. The state determination is made with
2-out-of-3 voting. The TX block uses the busy/idle
indication for arbitration. The STR bit of register
12HEX selects the words from stream A or stream B.
Forward voice channel data format.
Bit Sync
Word
1.Word
repeat
40
Word
Sync
11
Bit Sync
Word
Sync
2.Word
Bit Sync
37
Word
Sync
11
3.Word
repeat
40
Word
Sync
11
Sync
repeat
40
101
11
Bit Sync
37
9.Word
repeat
40
11
Bit Sync
Word
Sync
11
10.Word Bit Sync
repeat
11.Word
repeat
40
37
37
40
37
On the forward voice channel after bit synchronization
and word synchronization are received and the AUMUT
bit in register 13HEX is set to high, the RX audio block
will be muted until the 920 bits are received. The
repeated words are transferred to the voting block. The
voting is done bit by bit, 3-out-of-5. If three consecutive
words are identical, the receiver is powered down and
no remaining words are read. After the voting block the
data is transmitted to the BCH block. This block
performs decoding of the received BCH coded data.
The following polynomial is used:
If only one error occurs in data the BCH block can
correct it. If more than one error occurs the BCH block
cannot correct them and the BCHER bit of register
11HEX is set to high. The BCH block transfers the data
to the RX buffer. When the buffer is full the RXWRD bit
of register 10HEX is set to high and this causes interrupt
line XINT to go active. When register 10HEX is read the
interrupt is cleared. The data buffer can be read by
reading register 15HEX four times. If the next word is
coming and the previous word has not been read from
the buffer, the word is missed. The new and the old
words are compared.
G(x) = x12 + x10 + x8 + x5 + x4 + x3 + x0
12
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