MAS9187 参数 Datasheet PDF下载

DA9187.002

29 January, 2004

OPERATING MODES

DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)

(note: VREFL=GND in case of MAS9187A1). XRESET pin is used for middle code preset: DAC registers are

reset and middle code will appear at the DAC output.

Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.

Rising XCS-pin stops data reading and 12 CLK-cycles are used as the input data (4 address bits and 8 data

bits). The last 12 bits before rising XCS are used as input data.

◆

Timing diagram

SDI

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

CLK

XCS

V

OUT

APPLICATION AND TEST CIRCUIT INFORMATION

+3.0v

DAC Register Load

20

VDD

1

VREFH

MAS9187A2

8

XSHDN

O12

O11

CLK

SDI

XCS

O10

O9

O8

9

O7

O6

O5

O4

O3

19

18

17

16

15

14

7

6

5

4

3

2

Controller

Clock

Data In

Latch

12

13

100 nF

GND

10

O2

O1

VREFL

11

5 (7)